Product Specification
PE64101
UltraCMOS Digitally Tunable Capacitor
(DTC) 100 - 3000 MHz
Product Description
The PE64101 is a DuNE-enhanced Digitally Tunable
Features
Capacitor (DTC) based on Peregrines UltraCMOS
3-wire (SPI compatible) 8-bit serial interface
technology. DTC products provide a monolithically
with built-in bias voltage generation and
integrated impedance tuning solution for demanding RF
stand-by mode for reduced power
applications. They also offer a cost-effective tunable
consumption
capacitor with excellent linearity and ESD performance.
DuNE-enhanced UltraCMOS device
This highly versatile product can be mounted in series or
5-bit 32-state Digitally Tunable Capacitor
shunt configuration and is controlled by a 3-wire (SPI
C = 1.38 5.90 pF (4.3:1 tuning ratio) in
compatible) serial interface. High ESD rating of 2 kV
discrete 146 fF steps
HBM on all ports making this the ultimate in integration
RF power handling (up to 26 dBm, 6 V RF)
PK
and ruggedness. The DTC is offered in a standard 12-
and high linearity
lead 2.0 x 2.0 x 0.55 mm QFN package.
High quality factor
Peregrines DuNE technology enhancements deliver
Wide power supply range (2.3 to 3.6V) and
high linearity and exceptional harmonics performance. It
low current consumption
is an innovative feature of the UltraCMOS process,
(typ. I = 30 A @ 2.8V)
DD
providing performance superior to GaAs with the
Optimized for shunt configuration, but can
economy and integration of conventional CMOS.
also be used in series configuration
Excellent 2 kV HBM ESD tolerance on all
pins
Figure 1. Functional Block Diagram
Applications include:
Antenna tuning
Tunable filters
Phase shifters
Impedance matching
RF-
RF+
ESD ESD
Figure 2. Package Type
12-lead 2 x 2 x 0.55 mm QFN
CMOS Control
Serial
Interface
Driver and ESD
71-0066-01
Document No. 70-0378-01 www.psemi.com 2012 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE64101
Product Specification
Table 1. Electrical Specifications @ 25C, V = 2.8V
DD
Parameter Configuration Condition Min Typ Max Units
7
Operating Frequency Range Both 100 3000 MHz
6
Minimum Capacitance Shunt State = 00000, 100 MHz (RF+ to Grounded RF-) -10% 1.38 +10% pF
6
Maximum Capacitance Shunt State = 11111, 100 MHz (RF+ to Grounded RF-) -10% 5.90 +10% pF
6
Tuning Ratio Shunt C /C , 100 MHz 4.3:1
max min
6
Step Size Shunt 5 bits (32 states), constant step size (100 MHz) 0.146 pF
470 - 582 MHz with L removed 50
s
1 6
Quality Factor (C ) Shunt 698 - 960 MHz, with L removed 50
min s
1710 - 2170 MHz, with L removed 30
s
470 - 582 MHz with L removed 50
s
1 6
Quality Factor (C ) Shunt 698 - 960 MHz, with L removed 25
max s
1710 - 2170 MHz, with L removed 10
s
State 00000 5.5
7
Self Resonant Frequency Shunt GHz
State 11111 2.5
470 to 582 MHz, Pin +26 dBm, 50 -36 dBm
6
Shunt 698 to 915 MHz, Pin +26 dBm, 50 -36 dBm
1710 to 1910 MHz, Pin +26 dBm, 50 -36 dBm
4
Harmonics (2 and 3 )
fo fo
470 to 582 MHz, Pin +20 dBm, 50 -36 dBm
5
Series 698 to 915 MHz, Pin +20 dBm, 50 -36 dBm
1710 to 1910 MHz, Pin +20 dBm, 50 -36 dBm
IIP3 = (Pblocker + 2*Ptx - [IMD3]) / 2, where IMD3 = -95 dBm,
6
3rd Order Intercept Point Shunt 60 dBm
Ptx = +20 dBm and Pblocker = -15 dBm
State change to 10/90% delta capacitance between any two
2, 3 6
Switching Time Shunt 2 10 s
states
2 6 Time from V within specification to all performances within
DD
Start-up Time Shunt 5 20 s
specification
State change from standby mode to RF state to all
2, 3 6
Wake-up Time Shunt 5 20 s
performances within specification
Note: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit
Q = X / R = (X-X )/R, where X = X + X , X = 2*pi*f*L, X = -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance L
C L L C L C S
2. DC path to ground at RF+ and RF must be provided to achieve specified performance
3. State change activated on falling edge of SEN following data word
4. Between 50 ports in series or shunt configuration using a pulsed RF input with 4620 vs period, 50% duty cycle, measured per 3GPPTS45.005
5. In series configuration the greater RF power or higher RF voltage should be applied to RF+
6. RF- should be connected to ground
7. DTC operation above SRF is possible
2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 UltraCMOS RFIC Solutions
Page 2 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: