Document Type: Data Sheet ICS1893 Document Stage: Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General Features The ICS1893 is a low-power, physical-layer device (PHY) Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5 to that supports the ISO/IEC 10Base-T and 100Base-TX +85 C Carrier-Sense Multiple Access/Collision Detection DSP-based baseline wander correction to virtually (CSMA/CD) Ethernet standards. The ICS1893 architecture eliminate killer packets across temperature range of from is based on the ICS1892. The ICS1893 supports managed -5 to +85 C or unmanaged node, repeater, and switch applications. Low-power, 0.35-micron CMOS (typically 400 mW) Single 3.3-V power supply. The ICS1893 incorporates digital signal processing (DSP) in Single-chip, fully integrated PHY provides PCS, PMA, its Physical Medium Dependent (PMD) sublayer. As a result, PMD, and AUTONEG sublayers of IEEE standard it can transmit and receive data on unshielded twisted-pair 10Base-T and 100Base-TX IEEE 802.3 compliant (UTP) category 5 cables with attenuation in excess of 24 dB Fully integrated, DSP-based PMD includes: at 100 MHz. With this ICS-patented technology, the Adaptive equalization and baseline wander correction ICS1893 can virtually eliminate errors from killer packets. Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Highly configurable design supports: Management (STA) entity. Node, repeater, and switch applications Managed and unmanaged applications The ICS1893 Media Dependent Interface (MDI) can be 10M or 100M half- and full-duplex modes configured to provide either half- or full-duplex operation at Parallel detection data rates of 10 MHz or 100 MHz. The MDI configuration Auto-negotiation, with Next Page capabilities can be established manually (with input pins or control MAC/Repeater Interface can be configured as: register settings) or automatically (using th e 10M or 100M Media Independent Interface Auto-Negotiation features). When the ICS1893 100M Symbol Interface (bypasses the PCS) Auto-Negotiation sublayer is enabled, it exchanges 10M 7-wire Serial Interface technology capability data with its remote link partner and Small Footprint 64-pin Thin Quad Flat Pack (TQFP) automatically selects the highest-performance operating mode they have in common. ICS1893 Block Diagram 100Base-T PCS PMA TP PMD Frame Clock Recovery MLT-3 10/100 MII or Twisted- Interface Integrated CRS/COL Link Monitor Stream Cipher Alternate Detection Signal Detection Adaptive Equalizer Pair MUX Switch MAC/Repeater Parallel to Serial Error Detection Baseline Wander Interface to 4B/5B Correction Interface Magnetics Modules and 10Base-T RJ45 Connector MII Low-Jitter Configuration Auto- Extended MII Serial Clock Negotiation and Status Register Management Synthesizer Set Interface Clock Power LEDs and PHY Address ICS1893 Rev E 5/13/10 ICS reserves the right to make changes in the device data identified in June, 2000 this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.ICS1893 Data Sheet - Release Table of Contents Table of Contents Section Title Page Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 11 Chapter 2 Conventions and Nomenclature..................................................................................... 13 Chapter 3 ICS1893 Enhanced Features........................................................................................... 15 Chapter 4 Overview of the ICS1893.................................................................................................. 17 4.1 100Base-TX Operation ..........................................................................................18 4.2 10Base-T Operation ............................................................................................... 18 Chapter 5 Operating Modes Overview............................................................................................. 19 5.1 Reset Operations ................................................................................................... 20 5.1.1 General Reset Operations .....................................................................................20 5.1.2 Specific Reset Operations .....................................................................................21 5.2 Power-Down Operations ........................................................................................ 22 5.3 Automatic Power-Saving Operations ..................................................................... 23 5.4 Auto-Negotiation Operations .................................................................................. 23 5.5 100Base-TX Operations ........................................................................................ 24 5.6 10Base-T Operations ............................................................................................. 24 5.7 Half-Duplex and Full-Duplex Operations ............................................................... 24 Chapter 6 Interface Overviews.......................................................................................................... 25 6.1 MII Data Interface .................................................................................................. 26 6.2 100M Symbol Interface ..........................................................................................27 6.3 10M Serial Interface ............................................................................................... 29 6.4 Serial Management Interface ................................................................................. 31 6.5 Twisted-Pair Interface ............................................................................................31 6.5.1 Twisted-Pair Transmitter Interface .........................................................................32 6.5.2 Twisted-Pair Receiver Interface ............................................................................. 33 6.6 Clock Reference Interface .....................................................................................34 6.7 Configuration Interface ........................................................................................... 34 6.8 Status Interface ...................................................................................................... 35 Chapter 7 Functional Blocks............................................................................................................. 37 7.1 Functional Block: Media Independent Interface ..................................................... 38 7.2 Functional Block: Auto-Negotiation ........................................................................ 39 7.2.1 Auto-Negotiation General Process ........................................................................ 40 7.2.2 Auto-Negotiation: Parallel Detection ...................................................................... 41 7.2.3 Auto-Negotiation: Remote Fault Signaling ............................................................. 41 7.2.4 Auto-Negotiation: Reset and Restart ..................................................................... 42 7.2.5 Auto-Negotiation: Progress Monitor .......................................................................42 ICS1893 Rev C 6/6/00 June, 2000 Copyright 2000, Integrated Circuit Systems, Inc. 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