54FCT573TDB Renesas

IDT54/74FCT573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL IDT54/74FCT573T/AT/CT TRANSPARENT LATCH FEATURES: DESCRIPTION: Std., A, and C grades The FCT573Tis an octal transparent latch built using an advanced dual Low input and output leakage 1A (max.) metal CMOS technology. These octal latches have 3-state outputs and are CMOS power levels intended for bus oriented applications. The flip-flops appear transparent to True TTL input and output compatibility: the data when Latch Enable (LE) is high. When LE is low, the data that meets VOH = 3.3V (typ.) the set-up time is latched. Data appears on the bus when the Output Enable VOL = 0.3V (typ.) (OE) is low. When OE is high, the bus output is in the high-impedance state. High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permitlive insertio Available in the following packages: Industrial: SOIC, QSOP Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM D2 D3 D6 D7 D0 D1 D4 D5 D D D D D D D D O O O O O O O O G G G G G G G G LE OE O0 O1 O2 O3 O4 O5 O6 O7 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES NOVEMBER 2016 1 DSC-5948/8IDT54/74FCT573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH MILITARY AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION INDEX VCC 1 20 OE 19 2 O0 D0 3 2 20 19 D1 18 3 O1 1 4 18 O1 D2 D2 4 17 O2 5 17 O2 D3 D3 5 16 O3 6 16 D4 O3 D4 15 O4 6 7 15 D5 O4 D5 O5 D6 8 14 7 14 O5 9 10 11 12 13 D6 13 O6 8 D7 9 12 O7 LE 11 GND 10 CERDIP/ SOIC/ QSOP LCC TOP VIEW TOP VIEW (1) ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION Symbol Description Max Unit Pin Names Description (2) D x Data Inputs VTERM Terminal Voltage with Respect to GND 0.5 to +7 V (3) LE Latch Enable Input (Active HIGH) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V OE Output Enable Input (Active LOW) TSTG Storage Temperature 65 to +150 C O x 3-State Outputs IOUT DC Output Current 60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating (1) FUNCTION TABLE conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. Inputs Outputs 2. Inputs and Vcc terminals only. Dx LE OE Ox 3. Output and I/O terminals only. HH L H LH L L XX H Z CAPACITANCE (TA = +25C, F = 1.0MHz) NOTE: (1) 1. H = HIGH Voltage Level Symbol Parameter Conditions Typ. Max. Unit X = Dont Care CIN Input Capacitance VIN = 0V 6 10 pF L = LOW Voltage Level Z = High Impedance COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 1. This parameter is measured at characterization but not tested. 2 D7 D1 D0 GND OE LE O7 VCC O6 O0