551MLFT Renesas

DATASHEET 1 TO 4 CLOCK BUFFER ICS551 Description Features The ICS551 is a low cost, high-speed single input to Low skew (250 ps) outputs TM four output clock buffer. Part of IDTs ClockBlocks Pb-free packaging family, this is our lowest cost, small clock buffer. Low cost clock buffer See the ICS552-02B for monolithic dual version of the Packaged in 8-pin SOIC ICS551 in a 20 pin QSOP. Input/Output clock frequency up to 160 MHz Non-inverting output clock IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to Ideal for networking clocks synchronize clocks. Contact IDT for all of your clocking Operating Voltages of 3.3 and 5.0 V needs. Output Enable mode tri-states outputs Advanced, low power CMOS process Commercial and industrial temperature versions Block Diagram Q1 Q2 ICLK Q3 Q4 Output Enable IDT 1 TO 4 CLOCK BUFFER 1 ICS551 REV P 051310ICS551 1 TO 4 CLOCK BUFFER FAN OUT BUFFER Pin Assignment ICLK 1 8 OE Q1 2 7 VDD Q2 3 6 GND Q3 4 5 Q4 8 Pin (150 mil) SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK Input Clock input. Internal pull-up resistor. 2 Q1 Output Clock output 1. 3 Q2 Output Clock output 2. 4 Q3 Output Clock output 3. 5 Q4 Output Clock output 4. 6 GND Power Connect to ground. 7 VDD Power Connect to 3.3 V or 5.0 V. 8 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. IDT 1 TO 4 CLOCK BUFFER 2 ICS551 REV P 051310