VersaClock 6E Programmable 5P49V60 Clock Generator Datasheet Description Features Flexible 1.8V, 2.5V, 3.3V power-rails The 5P49V60 is a programmable clock generator intended for automotive applications. Configurations may be stored in on-chip High-performance, low phase noise PLL, < 0.5ps RMS typical 2 One-Time Programmable (OTP) memory or changed using I C phase jitter on outputs interface. This is Renesas sixth generation of programmable Four banks of internal OTP memory clock technology (VersaClock 6E). In-system or factory programmable The frequencies are generated from a single reference clock. The 2 select pins accessible with processor GPIOs or reference clock can come from one of the two redundant clock bootstrapping inputs. A glitchless manual switchover function allows one of the 2 I C serial programming interface redundant clocks to be selected during normal operation. 2 0xD0 or 0xD4 I C address options allows multiple devices Two select pins allow up to four different configurations to be configured in a same system programmed and accessible using processor GPIOs or Reference LVCMOS output clock bootstrapping. The different selections may be used for different Four universal output pairs individually configurable: operating modes (full function, partial function, partial Differential (LVPECL, LVDS or HCSL) power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use 2 single-ended (2 LVCMOS in-phase or 180 degrees out of 2 one of two I C addresses to allow multiple devices to be used in a phase) system. I/O V s can be mixed and matched, supporting 1.8V DD (LVDS and LVCMOS), 2.5V, or 3.3V Typical Applications Output frequency ranges: Automotive infotainment LVCMOS clock outputs: 1MHz to 200MHz LVDS, LVPECL, HCSL differential clock outputs: 1MHz to Dashboard systems 350MHz PCI Express 1.0 / 2.0 / 3.0 / 4.0 (with spread spectrum) Redundant clock inputs with manual switchover Audio/Video applications Programmable output enable or power-down mode Camera applications 4 4 mm 24-VFQFPN wettable flank package Active antennas AEC-Q100 qualified In-vehicle networking -40 to +105C (Grade 2) temperature operation Block Diagram VDDO0 XIN/REF OUT0 SEL I2CB VDDO1 XOUT OUT1 CLKIN FOD1 OUT1B CLKINB VDDO2 PLL CLKSEL OUT2 FOD2 SD/OE OTP OUT2B and SEL1/SDA VDDO3 Control SEL0/SCL Logic OUT3 V DDA FOD3 V OUT3B DDD VDDO4 OUT4 FOD4 OUT4B 2021 Renesas Electronics Corporation 1 March 16, 20215P49V60 Datasheet Contents Description 1 Typical Applications . 1 Features 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 3 Absolute Maximum Ratings . 5 Thermal Characteristics 5 Recommended Operating Conditions . 5 Electrical Characteristics . 6 I2C Bus Characteristics . 11 Test Loads . 12 Jitter Performance Characteristics . 13 PCI Express Jitter Performance and Specifications . 14 Features and Functional Blocks . 15 Device Startup and Power-On-Reset 15 Reference Clock and Selection . 15 Manual Switchover 15 Internal Crystal Oscillator (XIN/REF) 16 Choosing Crystals . 16 Tuning the Crystal Load Capacitor 16 Programmable Loop Filter . 17 Fractional Output Dividers (FOD) . 17 Individual Spread Spectrum Modulation 17 Bypass Mode 17 Dividers Alignment 17 Programmable Skew 17 Output Drivers 17 SD/OE Pin Function . 18 I2C Operation 18 Typical Application Circuits 19 Input Driving the XIN/REF or CLKIN . 20 Driving XIN/REF with a CMOS Driver 20 Driving XIN with an LVPECL Driver . 20 Wiring the CLKIN Pin to Accept Single-ended Inputs 21 Driving CLKIN with Differential Clock 21 Output Single-ended or Differential Clock Terminations 22 LVDS Termination 22 LVPECL Termination 23 HCSL Termination 24 LVCMOS Termination 25 Package Outline Drawings . 25 Marking Diagram 25 Ordering Information . 25 Revision History . 26 2021 Renesas Electronics Corporation 2 March 16, 2021