VersaClock 6E Programmable 5P49V6968 Clock Generator Datasheet Description Features The 5P49V6968 is a programmable clock generator that is Flexible 1.8V, 2.5V, and 3.3V power rails intended for high-performance consumer, networking, industrial, High-performance, low phase noise PLL, < 0.5ps RMS typical computing, and data communications applications. This is phase jitter on outputs Renesas sixth generation of programmable clock technology Four banks of internal OTP memory (VersaClock 6E). In-system or factory programmable The 5P49V6968 generates the frequencies from a single 2 I C serial programming interface reference clock, which can originate from one of the two 2 0xD0 or 0xD4 I C address options allow multiple devices to redundant clock inputs. A glitchless manual switchover function be configured in a same system allows one of the redundant clocks to be selected during normal operation. Reference LVCMOS output clock Three universal configurable outputs (OUT1, 2, 4): Two select pins allow up to four different configurations to be programmed, and can be used for different operating modes. Differential (LVPECL, LVDS, or HCSL) 1kHz to 350MHz Two single-ended (in-phase or 180 degrees out of phase) 1kHz to 200MHz Typical Applications I/O VDDs can be mixed and matched, supporting 1.8V Ethernet switch/router (LVDS and LVCMOS), 2.5V, or 3.3V PCI Express 1.0/2.0/3.0/4.0 spread spectrum on Independent spread spectrum on each output pair PCI Express 1.0/2.0/3.0/4.0/5.0 spread spectrum off Eight additional LPHCSL outputs (OUT 3, 511) Broadcast video/audio timing 1.8V low power supply Multi-function printer 1kHz to 200MHz Processor and FPGA clocking Programmable output enable or power-down mode Any-frequency clock conversion Redundant clock inputs with manual switchover MSAN/DSLAM/PON Available in 6 6 mm 48-VFQFPN package Fiber Channel, SAN -40 to +85C industrial temperature operation Telecom line cards Datacenter Block Diagram V 0 DDO XIN/REF OUT0 SEL I2CB VDDO1 OUT1 XOUT FOD1 OUT1B V 2 DDO CLKSEL OUT2 FOD2 SD/OE OTP OUT2B PLL and SEL1/SDA Control SEL0/SCL Logic OEA VDDA FOD3 OUT3, 5, 6, 11 VDDD OEB OUT7, 8, 9, 10 VDDO4 OUT4 FOD4 OUT4B 2020 Renesas Electronics Corporation 1 August 20, 2020 5P49V6968 Datasheet Contents 1. Pin Assignments ...........................................................................................................................................................................................3 2. Pin Descriptions ............................................................................................................................................................................................3 3. Absolute Maximum Ratings ..........................................................................................................................................................................6 4. Thermal Characteristics ................................................................................................................................................................................6 5. Recommended Operating Conditions...........................................................................................................................................................6 6. Electrical Characteristics ..............................................................................................................................................................................7 7. Test Loads ..................................................................................................................................................................................................14 8. Jitter Performance Characteristics..............................................................................................................................................................15 9. PCI Express Jitter Performance and Specification .....................................................................................................................................16 10. Features and Functional Blocks .................................................................................................................................................................18 10.1 Device Startup and Power-on-Reset ................................................................................................................................................18 10.2 Internal Crystal Oscillator (XIN/REF) ...............................................................................................................................................19 10.2.1 Choosing Crystals .............................................................................................................................................................19 10.2.2 Tuning the Crystal Load Capacitor ....................................................................................................................................19 10.3 Programmable Loop Filter................................................................................................................................................................21 10.4 Fractional Output Dividers (FOD) .....................................................................................................................................................21 10.4.1 Individual Spread Spectrum Modulation ...........................................................................................................................21 10.4.2 Bypass Mode ....................................................................................................................................................................21 10.4.3 Cascaded Mode ................................................................................................................................................................21 10.4.4 Dividers Alignment ............................................................................................................................................................21 10.4.5 Programmable Skew .........................................................................................................................................................22 10.5 Output Drivers ..................................................................................................................................................................................22 10.6 SD/OE Pin Function .........................................................................................................................................................................22 2 10.7 I C Operation ...................................................................................................................................................................................23 11. Typical Application Circuit ..........................................................................................................................................................................24 11.1 Input Driving the XIN/REF .............................................................................................................................................................25 11.1.1 Driving XIN/REF with a CMOS Driver ...............................................................................................................................25 11.1.2 Driving XIN with a LVPECL Driver ....................................................................................................................................26 11.2 Output Single-ended or Differential Clock Terminations ...............................................................................................................27 11.2.1 LVDS Termination .............................................................................................................................................................27 11.2.2 LVPECL Termination ........................................................................................................................................................28 11.2.3 HCSL Termination.............................................................................................................................................................29 11.2.4 LVCMOS Termination .......................................................................................................................................................29 12. Package Outline Drawings .........................................................................................................................................................................30 13. Marking Diagram .........................................................................................................................................................................................30 14. Ordering Information ...................................................................................................................................................................................30 15. Revision History ..........................................................................................................................................................................................31 2020 Renesas Electronics Corporation 2 August 20, 2020