HIGH-SPEED IDT7005S/L
8K x 8 DUAL-PORT
STATIC RAM
M/S = H for BUSY output flag on Master,
Features
M/S = L for BUSY input on Slave
True Dual-Ported memory cells which allow simultaneous
Interrupt Flag
reads of the same memory location
On-chip port arbitration logic
High-speed access
Full on-chip hardware support of semaphore signaling
Military: 20/25/35/55/70ns (max.)
between ports
Industrial: 35/55ns (max.)
Fully asynchronous operation from either port
Commercial:15/17/20/25/35/55ns (max.)
Devices are capable of withstanding greater than 2001V
Low-power operation
electrostatic discharge
IDT7005S
Battery backup operation2V data retention
Active: 750mW (typ.)
TTL-compatible, single 5V (10%) power supply
Standby: 5mW (typ.)
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
IDT7005L
thin quad flatpack
Active: 700mW (typ.)
Industrial temperature range (-40C to +85C) is available
Standby: 1mW (typ.)
for selected speeds
IDT7005 easily expands data bus width to 16 bits or more
Green parts available, see ordering information
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
OER
OEL
CEL CER
R/WL R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O I/O
Control Control
(1,2)
(1,2)
BUSYL
BUSYR
A12L A12R
Address MEMORY Address
Decoder ARRAY Decoder
A0L A0R
13
13
ARBITRATION
CEL
INTERRUPT CER
OEL SEMAPHORE
OER
LOGIC R/WR
R/WL
SEML SEMR
M/S
(2)
(2)
INTL INTR
2738 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
SEPTEMBER 2012
1
DSC 2738/17
2012 Integrated Device Technology, Inc.IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Description
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
Fabricated using CMOS high-performance technology, these de-
IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more vices typically operate on only 750mW of power. Low-power (L) versions
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach offer battery backup data retention capability with typical power consump-
tion of 500W from a 2V battery.
in 16-bit or wider memory system applications results in full-speed, error-
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control, flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military
address, and I/O pins that permit independent, asynchronous access for grade product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML making it ideally suited to military temperature applica-
reads or writes to any location in memory. An automatic power down
tions demanding the highest level of performance and reliability.
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
(1,2,3)
Pin Configurations
11/16/01
INDEX
987 6 5 4 3 21 68676665 64 63 62 61
I/O2L 60
10 A5L
I/O3L 59
11 A4L
I/O4L 58
12 A3L
57
I/O5L 13 A2L
56
GND 14 A1L
I/O6L IDT7005J or F 55 A0L
15
(4)
54
I/O7L J68-1
16 INTL
(4)
F68-1
VCC 53
17 BUSYL
GND 52
18 GND
68 Pin PLCC / FLATPACK
51
I/O0R 19
M/S
,
(5)
Top View
50
I/O1R 20 BUSYR
49
I/O2R INTR
21
VCC 48
22 A0R
I/O3R 47
23 A1R
46
I/O4R 24 A2R
45
I/O5R A3R
25
44
I/O6R
26 A4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2738 drw 02
11/16/01
INDEX
1 48 A4L
I/O2L
2 A3L
47
I/O3L
3 A2L
46
I/O4L
4 A1L
45
I/O5L
5
44 A0L
GND
6 INTL
7005PF 43
I/O6L
(4)
PN-64
7 BUSYL
I/O7L 42
8
GND
VCC 41
9 64-Pin TQFP
M/S
GND 40
.
(5)
Top View
10 BUSYR
I/O0R 39
I/O1R 11 INTR
38
12
NOTES: I/O2R 37 A0R
1. All VCC pins must be connected to power supply. VCC 13
A1R
36
2. All GND pins must be connected to ground supply. I/O3R 14
35 A2R
3. J68-1 package body is approximately .95 in x .95 in x .12 in.
I/O4R 15
34 A3R
F68-1 package body is approximately .97 in x .97 in x .08 in.
I/O5R 16
33 A4R
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2738 drw 03
6.42
2
I/O7R
I/O1L
N/C
I/O0L
OER
N/C
R/WR
OEL
SEMR
R/WL
CER
SEML
N/C
CEL
N/C
N/C
GND
N/C
A12R
VCC
A11R
A12L
A10R
A11L
A9R
A10L
A8R
A9L
A7R
A8L
A6R
A7L
A5R
A6L
I/O6R
17 64 I/O1L
18
63 I/O0L
I/O7R
19 62
OER OEL
20 61
R/WR R/WL
60
SEMR 21 SEML
22 59 CEL
CER
N/C 23 58 N/C
24
GND 57 VCC
25
56 A12L
A12R
A11R 26 55 A11L
A10R 27 A10L
54
28 53
A9R A9L
52 A8L
A8R 29
30 A7L
A7R
51
31 A6L
A6R 50
A5L
32 49
A5R