HIGH-SPEED IDT7007S/L 32K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than reads of the same memory location one device M/S = H for BUSY output flag on Master, High-speed access M/S = L for BUSY input on Slave Military: 25/35/55ns (max.) Industrial: 20/25/35/55ns (max.) Interrupt Flag Commercial: 15/20/25/35/55ns (max.) On-chip port arbitration logic Low-power operation Full on-chip hardware support of semaphore signaling between ports IDT7007S Fully asynchronous operation from either port Active: 850mW (typ.) Standby: 5mW (typ.) TTL-compatible, single 5V (10%) power supply IDT7007L Available in 68-pin PGA and PLCC and a 80-pin TQFP Industrial temperature range (40C to +85C) is available Active: 850mW (typ.) for selected speeds Standby: 1mW (typ.) IDT7007 easily expands data bus width to 16 bits or more Green parts available, see ordering information Functional Block Diagram OEL OER CEL CER R/WL R/WR I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYR BUSYL A14L A14R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 15 15 ARBITRATION CEL INTERRUPT CER OEL SEMAPHORE OER LOGIC R/WR R/WL SEMR SEML M/S (2) (2) INTR INTL 2940 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. OCTOBER 2008 1 2008 Integrated Device Technology, Inc. DSC 2940/13IDT7007S/L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges IDT7007S Description reads or writes to any location in memory. An automatic power down The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The feature controlled by CE permits the on-chip circuitry of each port to enter IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM a very LOW standby power mode. or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more Fabricated using IDTs CMOS high-performance technology, these word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach devices typically operate on only 850mW of power. in 16-bit or wider memory system applications results in full-speed, error- The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC, free operation without the need for additional discrete logic. and an 80-pin thin quad flatpack, TQFP. Military grade product is This device provides two independent ports with separate control, manufactured in compliance with the latest revision of MIL-PRF-38535 address, and I/O pins that permit independent, asynchronous access for QML, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. (1,2,3) Pin Configurations 11/06/01 INDEX 98 76 54 3 2 1 68676665 64 63 62 61 60 I/O2L A5L 10 59 I/O3L 11 A4L I/O4L 58 A3L 12 57 I/O5L A2L 13 56 GND 14 A1L 55 I/O6L A0L 15 IDT7007J 54 I/O7L INTL 16 (4) J68-1 53 BUSYL VCC 17 52 GND 18 GND 68-Pin PLCC 51 I/O0R 19 M/S (5) Top View 50 BUSYR I/O1R 20 49 I/O2R INTR 21 48 VCC 22 A0R 47 I/O3R 23 A1R I/O4R 46 24 A2R 45 I/O5R A3R 25 44 I/O6R 26 A4R 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2940 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately .95 in x .95 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. 2 I/O7R I/O1L N/C I/O0L OER N/C R/WR OEL SEMR R/WL CER SEML 4R A1 CEL A13R A14L GND A13L A12R VCC 1R A1 A12L A10R 11L A A9R A10L A8R A9L A7R A8L A6R A7L A5R A6L