HIGH-SPEED 7008S/L 64K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous IDT7008 easily expands data bus width to 16 bits or reads of the same memory location more using the Master/Slave select when cascading more High-speed access than one device Commercial: 15/25/35/55ns (max.) M/S = VIH for BUSY output flag on Master, Industrial: 20ns (max.) M/S = VIL for BUSY input on Slave Low-power operation Interrupt Flag IDT7008S On-chip port arbitration logic Active: 750mW (typ.) Full on-chip hardware support of semaphore signaling Standby: 5mW (typ.) between ports IDT7008L Fully asynchronous operation from either port Active: 750mW (typ.) TTL-compatible, single 5V (10%) power supply Standby: 1mW (typ.) Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP Dual chip enables allow for depth expansion without Industrial temperature range (40C to +85C) is available external logic for selected speeds Green parts available, see ordering information Functional Block Diagram R/WL R R/W CE0L CE0R CE1L CE1R OEL OER I/O I/O I/O0-7L I/O0-7R Control Control (1,2) (1,2) BUSY L BUSYR 64Kx8 A15L A15R Address MEMORY Address Decoder Decoder ARRAY A0R A0L 7008 16 16 ARBITRATION CE0L INTERRUPT CE0R SEMAPHORE CE1L CE1R LOGIC OEL OER L R/W R/WR SEML SEMR (2) (2) INTL INTR (1) M/S 3198 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). AUGUST 2019 1 DSC 3198/137008S/L High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM feature controlled by the chip enables (CE0 and CE1) permit the on-chip or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more circuitry of each port to enter a very low standby power mode. word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach Fabricated using a CMOS high-performance technology, these in 16-bit or wider memory system applications results in full-speed, error- devices typically operate on only 750mW of power. free operation without the need for additional discrete logic. The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA), This device provides two independent ports with separate control, a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad address, and I/O pins that permit independent, asynchronous access for Flatpack (TQFP). (1,2,3) Pin Configurations 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 A7L 33 11 A7R 34 A8L 10 A8R A9L 35 9 A9R 36 A10L A10R 8 A11L 37 A11R 7 38 A12L 6 A12R 39 A13L 5 A13R 40 A14L 4 A14R 41 A15L 3 A15R 42 NC 2 NC 7008 43 Vcc 1 GND (3,4) PLG84 44 NC 84 NC 45 NC 83 NC 46 CE0L 82 CE0R 47 CE1L 81 CE1R 48 SEML 80 SEMR 49 RIWL 79 R/WR OEL 50 78 OER 51 GND GND 77 52 GND 76 GND 53 NC 75 NC 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 3198 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. Package body is approximately 1.15 in x 1.15 in x .17 in. 3. This package code is used to reference the package diagram. 4. All GND pins must be connected to ground supply. 2 I/O 7L A6L I/O6L A5L I/O5L A4L I/O4L A3L I/O3L A2L I/O2L A1L GND A0L I/O1L NC I/O0L INTL Vcc BUSYL GND GND I/O0R M/S I/O1R BUSYR I/O2R INTR Vcc A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R I/O7R A5R NC A6R