CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations 18-Mbit density (1M 18, 512K 36) CY7C1319KV18 1M 18 CY7C1321KV18 512K 36 333-MHz clock for high bandwidth Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces (data transferred at CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous 666 MHz) at 333 MHz Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous Two input clocks (K and K) for precise DDR timing peripheral circuitry and a two-bit burst counter. Addresses for SRAM uses rising edges only read and write are latched on alternate rising edges of the input Two input clocks for output data (C and C) to minimize clock (K) clock. Write data is registered on the rising edges of both K skew and flight time mismatches and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Echo clocks (CQ and CQ) simplify data capture in high speed For CY7C1319KV18 and CY7C1321KV18, the burst counter systems takes in the least two significant bits of the external address and Synchronous internally self-timed writes bursts four 18-bit words in the case of CY7C1319KV18, and four 36-bit words in the case of CY7C1321KV18, sequentially into or DDR II operates with 1.5 cycle read latency when DOFF is out of the device. asserted HIGH Asynchronous inputs include an output impedance matching Operates similar to DDR I device with one cycle read latency input (ZQ). Synchronous data outputs (Q, sharing the same when DOFF is asserted LOW physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data 1.8 V core power supply with HSTL inputs and outputs separately from each individual DDR SRAM in the system Variable drive HSTL output buffers design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. Expanded HSTL output voltage (1.4 VV ) DD All synchronous inputs pass through input registers controlled by Supports both 1.5 V and 1.8 V I/O supply the K or K input clocks. All data outputs pass through output Available in 165-ball FBGA package (13 15 1.4 mm) registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip Offered in both Pb-free and non Pb-free packages synchronous self-timed write circuitry. JTAG 1149.1 compatible test access port For a complete list of related documentation, click here. Phase locked loop (PLL) for accurate data placement Selection Guide Description 333 MHz 250 MHz Unit Maximum operating frequency 300 250 MHz Maximum operating current 18 370 320 mA 36 440 370 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-58906 Rev. *K Revised December 19, 2017128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array 128K x 36 Array 256K x 18 Array CY7C1319KV18/CY7C1321KV18 Logic Block Diagram CY7C1319KV18 Burst A (1:0) Logic 2 Write Write Write Write 20 18 A Reg Reg Reg Reg (19:0) A Address (19:2) Register 18 LD K Output CLK R/W Logic K Gen. Control C DOFF Read Data Reg. C 72 V 18 REF 36 CQ Reg. Reg. Control R/W 18 CQ Logic 36 18 18 BWS 1:0 Reg. DQ 17:0 18 Logic Block Diagram CY7C1321KV18 Burst A (1:0) Logic 2 Write Write Write Write 19 17 A Reg Reg Reg Reg (18:0) A Address (18:2) Register 36 LD K Output CLK R/W Logic K Gen. Control C DOFF Read Data Reg. C 144 CQ V 72 36 REF Reg. Reg. Control CQ 36 R/W Logic 72 36 36 BWS 3:0 DQ Reg. 35:0 36 Document Number: 001-58906 Rev. *K Page 2 of 32 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode