CY7C1021D-10ZSXIT Infineon

CY7C1021D 1-Mbit (64 K 16) Static RAM 1-Mbit (64 K 16) Static RAM automatic power down feature that significantly reduces power Features consumption when deselected. The input and output pins (I/O 0 through I/O ) are placed in a high impedance state when the Temperature Ranges: 15 device is deselected (CE HIGH), outputs are disabled (OE Industrial: 40 C to 85 C HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during Automotive-A: 40 C to 85 C a write operation (CE LOW and WE LOW). Pin and Function Compatible with CY7C1021B Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data High Speed from I/O pins (I/O through I/O ), is written into the location 0 7 t = 10 ns AA specified on the address pins (A through A ). If Byte High 0 15 Low Active Power Enable (BHE) is LOW, then data from I/O pins (I/O through 8 I = 80 mA at 10 ns I/O ) is written into the location specified on the address pins CC 15 (A through A ). 0 15 Low CMOS Standby Power Read from the device by taking Chip Enable (CE) and Output I = 3 mA SB2 Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If 2.0 V Data Retention Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O to I/O . If 0 7 Automatic Power Down when Deselected Byte High Enable (BHE) is LOW, then data from memory CMOS for Optimum Speed and Power appears on I/O to I/O . See the Truth Table on page 10 for a 8 15 complete description of read and write modes. Independent Control of Upper and Lower Bits The CY7C1021D device is suitable for interfacing with Available in Pb-free 44-pin 400-Mil Wide Molded SOJ and processors that have TTL I/P levels. It is not suitable for 44-pin TSOP II Packages processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested Functional Description alternatives. The CY7C1021D is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an Logic Block Diagram DATA IN DRIVERS A 7 A 6 A 5 64K x 16 A 4 I/O I/O 0 7 RAM Array A 3 A I/O I/O 2 8 15 A 1 A 0 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05462 Rev. *M Revised June 19, 2013 ROW DECODER A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 SENSE AMPSCY7C1021D Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 11 Selection Guide ................................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 12 Operating Range ...............................................................4 Acronyms ........................................................................14 Electrical Characteristics .................................................4 Document Conventions ................................................. 14 Capacitance ......................................................................5 Units of Measure ....................................................... 14 Thermal Resistance ..........................................................5 Document History Page ................................................. 15 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 17 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 17 Data Retention Waveform ................................................6 Products ....................................................................17 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 17 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 17 Truth Table ......................................................................10 Technical Support ..................................................... 17 Document Number: 38-05462 Rev. *M Page 2 of 17