7009L HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master, reads of the same memory location M/S = VIL for BUSY input on Slave High-speed access Interrupt Flag On-chip port arbitration logic Commercial: 15/20ns (max.) Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7009L Fully asynchronous operation from either port TTL-compatible, single 5V (10%) power supply Active: 1W (typ.) Standby: 1mW (typ.) Available in a 100-pin TQFP Dual chip enables allow for depth expansion without Industrial temperature range (40C to +85C) is available external logic for selected speeds Green parts available, see ordering information IDT7009 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device Functional Block Diagram R/WL R/WR CE0L CE0R CE1L CE1R OE L OER I/O I/O I/O0-7L I/O 0-7R Control Control (1,2) (1,2) BUSY L BUSYR 128Kx8 A16L A16R Address Address MEMORY Decoder ARRAY Decoder A0R A0L 7009 17 17 ARBITRATION CE0L INTERRUPT CE0R SEMAPHORE CE1L CE1R LOGIC OEL R OE L R/W R R/W SEML SEMR (2) (2) INTL INTR (1) M/S 4839 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). MAY 2019 1 DSC-4839/97009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT7009 is a high-speed 128K x 8 Dual-Port Static RAM. The address, and I/O pins that permit independent, asynchronous access for IDT7009 is designed to be used as a stand-alone 1024K-bit Dual-Port reads or writes to any location in memory. An automatic power down RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or- feature controlled by the chip enables (CE0 and CE1) permit the on-chip more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM circuitry of each port to enter a very low standby power mode. approach in 16-bit or wider memory system applications results in full- Fabricated using a CMOS high-performance technology, these speed, error-free operation without the need for additional discrete logic. devices typically operate on only 1W of power. This device provides two independent ports with separate control, The IDT7009 is packaged in a 100-pin Thin Quad Flatpack (TQFP). (1,2,3) Pin Configurations 7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC 76 50 NC NC 77 49 NC 78 48 A6R NC 47 79 I/O7R A5R 80 46 I/O6R A4R 45 I/O5R A3R 81 44 I/O4R A2R 82 43 I/O3R A1R 83 42 Vcc A0R 84 41 I/O2R INTR 85 40 I/O1R BUSYR 86 39 I/O0R M/S 87 38 GND GND 88 7009 (4) 37 Vcc 89 PNG100 BUSYL 36 I/O0L INTL 90 35 91 I/O1L NC 34 GND 92 A0L 93 33 I/O2L A1L A2L 32 I/O3L 94 31 I/O4L A3L 95 30 I/O5L A4L 96 29 A5L I/O6L 97 A6L 28 I/O7L 98 99 27 NC NC 26 GND NC 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4839 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 NC NC NC NC A7L A7R A8L A8R A9L A9R A10L A10R A11L A11R A12L A12R A13L A13R A14L A14R A15L A15R A16L A16R Vcc GND NC NC NC NC NC NC NC NC CE0L CE0R CE1L CE1R SEML SEMR R/WL R/WR OEL OER GND GND NC GND NC NC