7014S12PFG Renesas

HIGH-SPEED 7014S 4K x 9DUAL-PORT STATIC RAM Features: Description: The IDT7014 is a high-speed 4K x 9 Dual-Port Static RAM designed True Dual-Ported memory cells which allow simultaneous reads of the same memory location to be used in systems where on-chip hardware port arbitration is not High-speed access needed. This part lends itself to high-speed applications which do not rely Commercial: 12ns (max.) on BUSY signals to manage simultaneous access. The IDT7014 provides two independent ports with separate control, Standard-power operation IDT7014S address, and I/O pins that permit independent, asynchronous access for Active: 750mW (typ.) reads or writes to any location in memory. See functional description. Fully asynchronous operation from either port The IDT7014 utilizes a 9-bit wide data path to allow for parity at the user s option. This feature is especially useful in data communication TTL-compatible single 5V (10%) power supply applications where it is necessary to use a parity bit for transmission/ Available in 52-pin PLCC and a 64-pin TQFP Green parts available, see ordering information reception error checking. Fabricated using a high-performance technology, these Dual-Ports typically operate on only 750mW of power at maximum access times as fast as 12ns. The IDT7014 is packaged in a 52-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Functional Block Diagram R/WL R/WR OER OEL I/O I/O I/O0R- I/O8R I/O0L- I/O8L CONTROL CONTROL ADDRESS MEMORY ADDRESS A0R-A11R A0L-A11L DECODER DECODER ARRAY 2528 drw 01 MAY 2019 1 DSC 2528/207014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range (1,2,3) Pin Configuration 20 19 18 17 16 15 14 13 12 11 10 9 8 I/O5L 21 7 A5L VCC 22 6 A4L I/O4L 23 5 A3L I/O3L 24 4 A2L 3 I/O2L A1L 25 7014 I/O1L 26 2 A0L (4) PLG52 I/O0L 27 A0R 1 I/O0R 28 52-Pin A1R 52 PLCC I/O1R 29 A2R 51 Top View I/O2R 30 A3R 50 I/O3R 31 49 A4R VCC 32 48 A5R I/O4R 33 47 A6R 34 35 36 37 38 39 40 41 42 43 44 45 46 2528 drw 02 46 45 44 43 42 4140 3938 37 36 35 3433 48 47 49 32 A5R I/O5R 31 50 I/O4R A4R 30 A3R 51 VCC 29 A2R 52 I/O3R A1R 53 28 I/O2R A0R 54 27 I/O1R 7014 N/C 55 26 I/O0R (4) PNG64 56 25 N/C GND N/C 24 57 GND 64-Pin N/C 58 23 I/O0L TQFP 59 A0L 22 I/O1L Top View 60 A1L 21 I/O2L A2L 61 20 I/O3L A3L 62 19 I/O4L A4L 63 18 VCC A5L 64 17 I/O5L 1 2 3 4 5 6 7 8 9 10 11 12 131415 16 2528 drw 03 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply PLG52 package body is approximately .75 in x .75 in. x .17 in. 3 PNG64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 I/O5R I/O6L I/O6R I/O7L I/O7R I/O8L I/O8R GND GND R/WL R/WR VCC GND OEL OER A11L A11R A10L A10R A9L A9R A8L A6L A6R A8R A7L A7L A7R A7R A6L A8L A8R A9L A9R A10L A10R A11L A11R OEL OER N/C N/C VCC GND N/C N/C R/WL R/WR N/C N/C GND GND I/O8L I/O8R I/O7L I/O7R I/O6L I/O6R