HIGH-SPEED IDT7024S/L 4K x 16 DUAL-PORT STATIC RAM IDT7024 easily expands data bus width to 32 bits or more Features using the Master/Slave select when cascading more than True Dual-Ported memory cells which allow simultaneous one device reads of the same memory location M/S = H for BUSY output flag on Master High-speed access M/S = L for BUSY input on Slave Military: 20/25/35/55/70ns (max.) Interrupt Flag Industrial: 55ns (max.) On-chip port arbitration logic Commercial: 15/17/20/25/35/55ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7024S Fully asynchronous operation from either port Active: 750mW (typ.) Battery backup operation2V data retention Standby: 5mW (typ.) TTL-compatible, single 5V (10%) power supply IDT7024L Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Active: 750mW (typ.) Quad Flatpack Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Separate upper-byte and lower-byte control for multiplexed for selected speeds bus compatibility Green parts availble, see ordering information Functional Block Diagram L R R/W R/W UBR UBL LBL LBR CER CEL OER OEL I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R (1,2) (1,2) BUSYL BUSYR A11R A11L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 12 12 ARBITRATION CER CEL INTERRUPT OER OEL SEMAPHORE LOGIC R/WR R/WL SEMR SEML (2) (2) M/S INTR INTL 2740 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. JUNE 2013 1 DSC 2740/14 2013 Integrated Device Technology, Inc.IDT7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The port to enter a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM devices typically operate on only 750mW of power. Low-power (L) or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach versions offer battery backup data retention capability with typical power in 32-bit or wider memory system applications results in full-speed, error- consumption of 500W from a 2V battery. free operation without the need for additional discrete logic. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack and PLCC, and a 100-pin TQFP. Military grade product is manufactured This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for in compliance with the latest revision of MIL-PRF-38535 QML, making it reads or writes to any location in memory. An automatic power down ideally suited to military temperature applications demanding the highest feature controlled by chip enable (CE) permits the on-chip circuitry of each level of performance and reliability. (1,2,3) Pin Configurations INDEX 11/06/01 1110 98 7654 32 18483 82 81 80 79 78 77 76 75 I/O8L A7L 12 74 A6L I/O9L 73 13 I/O10L A5L 14 72 A4L I/O11L 71 15 A3L I/O12L 16 70 A2L I/O13L 69 17 A1L GND 68 18 IDT7024J or F A0L I/O14L 67 19 (4) J84-1 INTL I/O15L (4) 66 20 F84-2 VCC BUSYL 21 65 84-Pin PLCC / Flatpack GND GND 64 22 (5) Top View I/O0R 23 63 M/S I/O1R 62 24 BUSYR I/O2R 25 61 INTR VCC 60 26 A0R I/O3R 27 59 A1R I/O4R 58 28 A2R I/O5R 29 57 A3R I/O6R 56 30 A4R I/O7R 31 55 A5R I/O8R 54 A6R 32 Index 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 , 2740 drw 02 11/06/01 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 N/C 1 75 N/C N/C 2 74 N/C N/C 3 73 N/C 4 72 N/C N/C I/O10L 5 71 A5L I/O11L 6 70 A4L I/O12L 7 69 A3L I/O13L 8 68 A2L GND 9 67 A1L I/O14L 10 66 A0L IDT7024PF I/O15L 11 65 INTL (4) PN100-1 VCC 12 64 BUSYL GND 13 63 GND 100-Pin TQFP 62 I/O0R 14 M/S (5) Top View 61 I/O1R 15 BUSYR I/O2R 16 60 INTR 59 VCC 17 A0R 58 I/O3R 18 A1R I/O4R 19 57 A2R 56 I/O5R 20 A3R 55 I/O6R 21 A4R NOTES: N/C 22 54 N/C 1. All VCC pins must be connected to the power supply. 53 N/C 23 N/C 52 N/C 24 N/C 2. All GND pins must be connected to the ground supply. 51 N/C 25 N/C 3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 F84-2 package body is approximately 1.17 in x 1.17 in x .11 in. 2740 drw 03 PN100-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 I/O9R I/O7L I/O10R I/O 6L I/O11R I/O5L I/O12R I/O4L I/O13R I/O3L I/O14R I/O2L GND GND I/O15R I/O1L OER I/O0L R/WR OEL GND VCC SEMR R/WL CER SEML UBR CEL LBR UBL N/C LBL A11R N/C A10R A11L A9R A10L A8R A9L A7R A8L I/O7R I/O9L I/O8R I/O8L I/O9R I/O7L I/O10R I/O6L I/O11R I/O5L I/O12R I/O4L I/O13R I/O3L I/O14R I/O2L GND GND I/O15R I/O1L I/O0L OER R/WR OEL GND VCC R/WL SEMR CER SEML UBR CEL UBL LBR LBL N/C A11R N/C A11L A10R A10L A9R A8R A9L A8L A7R A6R A7L A5R A6L