HIGH-SPEED 2.5V 70T3539M 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: Data input, address, byte enable and control registers True Dual-Port memory cells which allow simultaneous Self-timed write allows fast cycle time access of the same memory location Separate byte controls for multiplexed bus and bus High-speed data access matching compatibility Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.) Dual Cycle Deselect (DCD) for Pipelined Output Mode Industrial: 4.2ns (133MHz) (max.) 2.5V (100mV) power supply for core Selectable Pipelined or Flow-Through output mode LVTTL compatible, selectable 3.3V (150mV) or 2.5V Counter enable and repeat features (100mV) power supply for I/Os and control signals on Dual chip enables allow for depth expansion without each port additional logic Includes JTAG functionality Interrupt and Collision Detection Flags Industrial temperature range (-40C to +85C) is Full synchronous operation on both ports available at 133MHz 6ns cycle time, 166MHz operation (12Gbps bandwidth) Available in a 256-pin Ball Grid Array (BGA) Fast 3.6ns clock to data out Green parts available, see ordering information 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs 166MHz Functional Block Diagram BE3R BE3L BE2L BE2R BE1L BE1R BE0L BE0R FT/PIPEL 0a 1a 0b 1b 0c 1c 0d 1d 1d 0d 1c 0c 1b 0b 1a 0a FT/PIPER 1/0 1/0 abc d dc b a R/WL R/WR CE0L CE0R 1 1 CE1R CE1L 0 0 B B B B B B B B 1/0 1/0 W W W W W W W W 0 1 2 3 3 2 1 0 L L L L R R R R OER OEL Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R , 1d 0d 1c 0c 1b 0b 1a 0a 0a 1a 0b 1b 0c 1c 0d 1d FT/PIPEL 0/1 0/1 FT/PIPER abcd dc ba 512K x 36 MEMORY ARRAY I/O0L - I/O35L I/O0R - I/O35R Din L Din R , CLKR CLKL A18L A18R Counter/ Counter/ A A0L 0R ADDR L ADDR R REPEATL Address REPEATR Address ADSR ADSL Reg. Reg. CNTENL CNTENR TDI TCK INTERRUPT CE0 R TMS CE 0 L JTAG COLLISION CE1 R TRST CE1L TDO DETECTION R/WL R/W LOGIC R COL L COL R INTL INTR (1) ZZ (1) ZZL ZZR CONTROL 5678 drw 01 LOGIC NOTE: 1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. JUNE 2019 1 DSC 5678/1070T3539M High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70T3539M is a high-speed 512K x 36 bit synchronous Dual- in bursts. An automatic power down feature, controlled by CE0 and CE1, Port RAM. The memory array utilizes Dual-Port memory cells to allow permits the on-chip circuitry of each port to enter a very low standby power simultaneous access of any address from both ports. Registers on control, mode. data, and address inputs provide minimal setup and hold times. The timing The 70T3539M can support an operating voltage of either 3.3V or latitude provided by this approach allows systems to be designed with very 2.5V on one or both ports, controllable by the OPT pins. The power supply short cycle times. With an input data register, the IDT70T3539M has been for the core of the device (VDD) is at 2.5V. optimized for applications having unidirectional or bidirectional data flow 6.422