HIGH-SPEED 2.5V 70T3719/99M 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: True Dual-Port memory cells which allow simultaneous 1.7ns setup to clock and 0.5ns hold on all control, data, and access of the same memory location address inputs 166MHz High-speed data access Data input, address, byte enable and control registers Commercial: 3.6ns (166MHz) Separate byte controls for multiplexed bus and bus 4.2ns (133MHz)(max.) matching compatibility Industrial: 4.2ns (133MHz) (max.) Dual Cycle Deselect (DCD) for Pipelined Output Mode Selectable Pipelined or Flow-Through output mode 2.5V (100mV) power supply for core Counter enable and repeat features LVTTL compatible, selectable 3.3V (150mV) or 2.5V Dual chip enables allow for depth expansion without (100mV) power supply for I/Os and control signals on additional logic each port Interrupt and Collision Detection Flags Industrial temperature range (-40C to +85C) is Full synchronous operation on both ports available at 133MHz 6ns cycle time, 166MHz operation (23.9Gbps bandwidth) Available in a 324-pin Green Ball Grid Array (BGA) Fast 3.6ns clock to data out Includes JTAG Functionality Self-timed write allows fast cycle time Green parts available, see ordering information Functional Block Diagram BE7R BE7L BE0L BE0R FT/PIPEL 0a 1a 0h 1h 1h 0h 1a 0a FT/PIPER 1/0 1/0 ha ah R/WL R/WR CE0L CE0R 1 1 CE1R CE1L 0 0 B B B B 1/0 1/0 W W W W 0 7 7 0 L L R R OER OEL DOUT0-8 L DOUT0-8 R DOUT9-17 L DOUT9-17 R DOUT18-26 L DOUT18-26 R DOUT27-35 L DOUT27-35 R DOUT36-44 L DOUT36-44 R DOUT45-53 L DOUT45-53 R DOUT54-62 L DOUT54-62 R DOUT63-72 L DOUT63-72 R , 1h 0h 1a 0a 0a 1a 0h 1h FT/PIPEL 0/1 0/1 FT/PIPER ah ha 256/128K x 72 MEMORY ARRAY Byte 0 Byte 7 Byte 7 Byte 0 I/O0L - I/O71L DIN L I/O0R - I/O71R DIN R , CLKL CLKR (1) A17L (1) A17R A0L Counter/ Counter/ A R 0 ADDR L ADDR R REPEATL Address REPEATR Address ADSL Reg. ADSR Reg. CNTENR CNTENL INTERRUPT CE0L CE0R TDI TCK COLLISION CE1L CE1R TMS JTAG DETECTION TDO TRST R/WL LOGIC R/WR COL L R COL INTL INTR (2) ZZ (2) ZZL ZZR CONTROL LOGIC 5687 drw 01 NOTES: 1. Address A17 is a NC for the IDT70T3799. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx NOVEMBER 2019 and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 1 DSC 5687/6 2019 Integrated Device Technology, Inc.70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchro- tional or bidirectional data flow in bursts. An automatic power down feature, nous Dual-Port RAM. The memory array utilizes Dual-Port memory cells controlled by CE0 and CE1, permits the on-chip circuitry of each port to to allow simultaneous access of any address from both ports. Registers on enter a very low standby power mode. control, data, and address inputs provide minimal setup and hold times. The 70T3719/99M can support an operating voltage of either 3.3V The timing latitude provided by this approach allows systems to be or 2.5V on one or both ports, controllable by the OPT pins. The power designed with very short cycle times. With an input data register, the supply for the core of the device (VDD) is at 2.5V. IDT70T3719/99M has been optimized for applications having unidirec- 6.422