70T633S12BFI Renesas

70T633/1S HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features Full hardware support of semaphore signaling between True Dual-Port memory cells which allow simultaneous ports on-chip access of the same memory location Fully asynchronous operation from either port High-speed access Separate byte controls for multiplexed bus and bus Commercial: 10/12/15ns (max.) matching compatibility Industrial: 10/12ns (max.) Sleep Mode Inputs on both ports RapidWrite Mode simplifies high-speed consecutive write Supports JTAG features compliant to IEEE 1149.1 in cycles BGA-208 and BGA-256 packages Dual chip enables allow for depth expansion without Single 2.5V (100mV) power supply for core external logic LVTTL-compatible, selectable 3.3V (150mV)/2.5V (100mV) IDT70T633/1 easily expands data bus width to 36 bits or power supply for I/Os and control signals on each port more using the Master/Slave select when cascading more Available in a 256-ball Ball Grid Array and 208-ball fine pitch than one device Ball Grid Array M/S = VIH for BUSY output flag on Master, Industrial temperature range (40C to +85C) is available M/S = VIL for BUSY input on Slave for selected speeds Busy and Interrupt Flags Green parts available, see ordering information On-chip port arbitration logic Functional Block Diagram UBL UBR LBL LBR R/WL R/WR B B B B E E E E 0 1 1 0 CE0L CE0R L L R R CE1L CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R 512/256K x 18 MEMORY ARRAY Din L I/O0L-I/O17L Din R I/O0R - I/O17R (1) A18R (1) A18L Address Address ADDR L ADDR R Decoder Decoder A0R A0L TDI TCK TMS JTAG OEL ARBITRATION OER TDO TRST INTERRUPT CE0R CE0L SEMAPHORE CE1R CE1L LOGIC R/WL R/WR (2,3) (2,3) BUSYL BUSYR M/S SEML SEMR (3) (3) INTL INTR (4) ZZ (4) ZZL ZZR NOTES: CONTROL LOGIC 1. Address A18x is a NC for IDT70T631. 5670 drw 01 2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 3 BUSY and INT are non-tri-state totem-pole outputs (push-pull). 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. AUGUST 2019 1 2019 Integrated Device Technology, Inc. DSC-5670/1170T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous feature controlled by the chip enables (either CE0 or CE1) permit the Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a on-chip circuitry of each port to enter a very low standby power mode. stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS- The IDT70T633/1 has a RapidWrite Mode which allows the designer TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the to perform back-to-back write operations without pulsing the R/W input IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider each cycle. This is especially significant at the 10ns cycle times of the memory system applications results in full-speed, error-free operation IDT70T633/1, easing design considerations at these high performance without the need for additional discrete logic. levels. This device provides two independent ports with separate control, The 70T633/1 can support an operating voltage of either 3.3V or 2.5V address, and I/O pins that permit independent, asynchronous access for on one or both ports, controlled by the OPT pins. The power supply for reads or writes to any location in memory. An automatic power down the core of the device (VDD) remains at 2.5V. 2