70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE On-chip port arbitration logic Features Full on-chip hardware support of semaphore signaling True Dual-Port memory cells which allow simultaneous between ports access of the same memory location Fully asynchronous operation from either port High-speed access Separate byte controls for multiplexed bus and bus Commercial: 10/12/15ns (max.) matching compatibility Industrial: 10/12ns (max.) Sleep Mode Inputs on both ports RapidWrite Mode simplifies high-speed consecutive write Supports JTAG features compliant to IEEE 1149.1 cycles Single 2.5V (100mV) power supply for core Dual chip enables allow for depth expansion without LVTTL-compatible, selectable 3.3V (150mV)/2.5V (100mV) external logic power supply for I/Os and control signals on each port IDT70T651/9 easily expands data bus width to 72 bits or Available in a 256-ball Ball Grid Array and 208-ball fine pitch more using the Master/Slave select when cascading more Ball Grid Array than one device Industrial temperature range (40C to +85C) is available M/S = VIH for BUSY output flag on Master, for selected speeds M/S = VIL for BUSY input on Slave Green parts available, see ordering information Busy and Interrupt Flags Functional Block Diagram BE3L BE3R BE2L BE2R BE1L BE1R BE0L BE0R R/WL R/WR B B B B B B B B E E E E E E E E 0 1 2 3 3 2 1 0 CE0L CE0R L L L L R R R R CE1L CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R 256/128K x 36 MEMORY ARRAY I/O0L- I/O35L Di n L Di n R I/O0R -I/O35R (1) (1) A17R Address A17L Address ADDR L ADDR R Decoder Decoder A0R A0L CE0L ARBITRATION CE0R TDI TCK CE1L TMS INTERRUPT CE1R JTAG TDO TRST OEL OER SEMAPHORE LOGIC R/WL R/WR (2,3) BUSYL (2,3) BUSYR SEML M/S SEMR (3) (3) INTL INTR ZZ (4) (4) ZZL ZZR CONTROL NOTES: LOGIC 1. Address A17x is a NC for IDT70T659. 2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 3. BUSY and INT are non-tri-state totem-pole outputs (push-pull). 4869 drw 01 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. MAY 2019 1 2019 Integrated Device Technology, Inc. DSC-5632/1070T651/9S High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous feature controlled by the chip enables (either CE0 or CE1) permit the Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a on-chip circuitry of each port to enter a very low standby power mode. stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS- The IDT70T651/9 has a RapidWrite Mode which allows the designer TER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the to perform back-to-back write operations without pulsing the R/W input IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider each cycle. This is especially significant at the 10ns cycle time of the memory system applications results in full-speed, error-free operation IDT70T651/9, easing design considerations at these high performance without the need for additional discrete logic. levels. This device provides two independent ports with separate control, The 70T651/9 can support an operating voltage of either 3.3V or 2.5V address, and I/O pins that permit independent, asynchronous access for on one or both ports, controlled by the OPT pins. The power supply for reads or writes to any location in memory. An automatic power down the core of the device (VDD) is at 2.5V. 2