GS8342DT07/10/19/37BD-450/400/350/333/300 450 MHz300 MHz 165-Bump BGA TM 36Mb SigmaQuad-II+ 1.8 V V Commercial Temp DD Industrial Temp Burst of 4 SRAM 1.8 V and 1.5 V I/O are just one element in a family of low power, low voltage Features HSTL I/O SRAMs designed to operate at the speeds needed to 2.0 Clock Latency implement economical high performance networking systems. Simultaneous Read and Write SigmaQuad Interface JEDEC-standard pinout and package Dual Double Data Rate interface Clocking and Addressing Schemes Byte Write controls sampled at data-in time Burst of 4 Read and Write The GS8342DT07/10/19/37BD SigmaQuad-II+ SRAMs are Dual-Range On-Die Termination (ODT) on Data (D), Byte synchronous devices. They employ two input register clock Write (BW), and Clock (K, K) inputs inputs, K and K. K and K are independent single-ended clock 1.8 V +100/100 mV core power supply inputs, not differential inputs to a single differential clock input 1.5 V or 1.8 V HSTL Interface buffer. Pipelined read operation Fully coherent read and write pipelines Each internal read and write operation in a SigmaQuad-II+ B4 ZQ pin for programmable output drive strength RAM is four times wider than the device I/O bus. An input Data Valid Pin (QVLD) Support data bus de-multiplexer is used to accumulate incoming data IEEE 1149.1 JTAG-compliant Boundary Scan before it is simultaneously written to the memory array. An 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package output data multiplexer is used to capture the data produced RoHS-compliant 165-bump BGA package available from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II+ B4 RAM is always two address pins SigmaQuad Family Overview less than the advertised index depth (e.g., the 4M x 8 has a 1M The GS8342DT07/10/19/37BD are built in compliance with addressable index). the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342DT07/10/19/37BD SigmaQuad SRAMs Parameter Synopsis -450 -400 -350 -333 -300 tKHKH 2.22 ns 2.5 ns 2.86 ns 3.0 ns 3.3 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.01a 8/2017 1/29 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8342DT07/10/19/37BD-450/400/350/333/300 4M x 8 SigmaQuad-II SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA A CQ SA W NW1 K R SA SA CQ (72Mb) (144Mb) NC/SA B NC NC NC SA K NW0 SA NC NC Q3 (288Mb) C NC NC NC V SA NC SA V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC D5 Q5 V V V V V NC NC NC DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC NC V V V V V NC Q1 D1 DDQ DD SS DD DDQ K NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ L NC Q6 D6 V V V V V NC NC Q0 DDQ SS SS SS DDQ M NC NC NC V V V V V NC NC D0 SS SS SS SS SS N NC D7 NC V SA SA SA V NC NC NC SS SS P NC NC Q7 SA SA QVLD SA SA NC NC NC R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. Pins A2, A7, and B5 are the expansion addresses. Rev: 1.01a 8/2017 2/29 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see