70T653MS12BCI Renesas

70T653M HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features True Dual-Port memory cells which allow simultaneous Full on-chip hardware support of semaphore signaling access of the same memory location between ports High-speed access Fully asynchronous operation from either port Commercial: 10/12/15ns (max.) Separate byte controls for multiplexed bus and bus Industrial: 12ns (max.) matching compatibility RapidWrite Mode simplifies high-speed consecutive write Sleep Mode Inputs on both ports cycles Single 2.5V (100mV) power supply for core Dual chip enables allow for depth expansion without LVTTL-compatible, selectable 3.3V (150mV)/2.5V (100mV) external logic power supply for I/Os and control signals on each port IDT70T653M easily expands data bus width to 72 bits or Includes JTAG functionality more using the Busy Input when cascading more than one Available in a 256-ball Ball Grid Array device Industrial temperature range (40C to +85C) is available Busy input for port contention management for selected speeds Interrupt Flags Green parts available, see ordering information Functional Block Diagram BE3L BE3R BE2L BE2R BE1L BE1R BE0L BE0R R/WL R/WR B B B B B B B B E E E E E E E E 0 1 2 3 3 2 1 0 CE0L CE0R L L L L R R R R CE1L CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R 512K x 36 MEMORY ARRAY I/O0L- I/O35L Di n L Di n R I/O0R -I/O35R A18R Address A18L Address ADDR L ADDR R Decoder Decoder A0R A0L CE0L ARBITRATION CE0R TDI TCK CE1L TMS INTERRUPT CE1R JTAG TDO TRST OEL OER SEMAPHORE LOGIC R/WL R/WR BUSYL BUSYR SEML SEMR (1) (1) INTL INTR ZZ NOTES: (2) (2) ZZL CONTROL ZZR LOGIC 1. INT is non-tri-state totem-pole outputs (push-pull). 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 5679 drw 01 JUNE 2019 1 DSC-5679/870T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70T653M is a high-speed 512K x 36 Asynchronous Dual- The IDT70T653M has a RapidWrite Mode which allows the designer Port Static RAM. The IDT70T653M is designed to be used as a stand- to perform back-to-back write operations without pulsing the R/W input alone 18874K-bit Dual-Port RAM. This device provides two independent each cycle. This is especially significant at the 10ns cycle time of the ports with separate control, address, and I/O pins that permit independent, IDT70T653M, easing design considerations at these high performance asynchronous access for reads or writes to any location in memory. An levels. automatic power down feature controlled by the chip enables (either CE0 The 70T653M can support an operating voltage of either 3.3V or 2.5V or CE1) permit the on-chip circuitry of each port to enter a very low standby on one or both ports, controlled by the OPT pins. The power supply for power mode. the core of the device (VDD) is at 2.5V. 2