HIGH-SPEED 3.3V 70V05S/L 8K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master reads of the same memory location M/S = VIL for BUSY input on Slave High-speed access Interrupt Flag Commercial: 15ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT70V05L Fully asynchronous operation from either port Active: 380mW (typ.) TTL-compatible, single 3.3V (0.3V) power supply Standby: 660W (typ.) Available in 68-pin PLCC and a 64-pin TQFP IDT70V05 easily expands data bus width to 16 bits or more Industrial temperature range (-40C to +85C) is available using the Master/Slave select when cascading more than for selected speeds one device Green parts available, see ordering information Functional Block Diagram OEL OER CEL CER L R/W R/WR , I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A12L A12R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 13 13 ARBITRATION CEL INTERRUPT CER SEMAPHORE OEL OER LOGIC R/WR R/WL SEML SEMR M/S (2) (2) INTL INTR 2942 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. JUNE 2019 1 DSC 2941/1270V05L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description reads or writes to any location in memory. An automatic power down The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The feature controlled by CE permits the on-chip circuitry of each port to enter IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port a very low standby power mode. SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit- Fabricated using CMOS high-performance technology, these de- or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM vices typically operate on only 400mW of power. approach in 16-bit or wider memory system applications results in full- The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC speed, error-free operation without the need for additional discrete logic. and a 64-pin thin quad flatpack (TQFP). This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for (1,2,3) Pin Configurations 10 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 I/O1L I/O7R 27 8 I/O0L 28 N/C 7 N/C OER 29 6 OEL R/WR 30 5 R/WL 31 SEMR 4 SEML 32 CER 3 CEL N/C 33 70V05 2 N/C 34 N/C (4) PLG68 35 1 VSS N/C 68-Pin PLCC 68 VDD A12R 36 Top View 37 67 A12L A11R 66 A10R 38 A11L 39 65 A10L A9R 40 64 A8R A9L 41 63 A7R A8L 42 A6R 62 A7L 43 61 A5R A6L 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2941 drw 02 44 43 42 41 40 39 48 47 46 45 38 37 36 35 34 33 32 A5R A5L 49 31 A6L 50 A6R A7L 51 30 A7R A8L 52 29 A8R A9R A9L 53 28 A10L 54 27 A10R 55 A11R A11L 26 70V05 56 25 A12R A12L (4) PNG64 VDD 57 24 GND N/C 58 23 N/C 64-Pin TQFP CEL 59 22 CER Top View SEML 60 21 SEMR R/WL 61 20 R/WR OEL 62 19 OER I/O0L 63 18 I/O7R NOTES: I/O1L 64 17 I/O6R 1. All VCC pins must be connected to power supply. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2. All GND pins must be connected to ground supply. 3. J68-1 package body is approximately .95 in x .95 in x .17 in. 2941 drw 03 PN64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.422 A4R I/O6R A3R I/O5R A2R I/O4R A1R I/O3R A0R VDD INTR I/O2R BUSYR I/O1R I/O0R M/S VSS VSS VDD BUSYL I/O7L INTL A0L I/O6L VSS A1L I/O5L A2L I/O4L A3L A4L I/O3L A5L I/O2L A4L I/O2L A3L I/O3L A2L I/O4L A1L I/O5L A0L VSS INTL I/O6L BUSYL I/O7L VSS VDD M/S VSS BUSYR I/O0R INTR I/O1R A0R I/O2R A1R VDD A2R I/O3R I/O4R A3R A4R I/O5R