CY7C1049G CY7C1049GE 4-Mbit (512K words 8-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (512K words 8-bit) Static RAM with Error-Correcting Code (ECC) offered in single and dual chip-enable options and in multiple pin Features configurations. The CY7C1049GE device includes an ERR pin High speed that signals an error-detection and correction event during a read t = 10 ns cycle. AA 1, 2 Embedded ECC for single-bit error correction Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O 0 Low active and standby currents through I/O and address on A through A pins. 7 0 18 Active current: I = 38 mA typical CC Data reads are performed by asserting the Chip Enable (CE) and Standby current: I = 6 mA typical SB2 Output Enable (OE) inputs LOW and providing the required Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and address on the address lines. Read data is accessible on the I/O 4.5 V to 5.5 V lines (I/O through I/O ). 0 7 1.0-V data retention All I/Os (I/O through I/O ) are placed in a high-impedance state 0 7 during the following events: TTL-compatible inputs and outputs The device is deselected (CE HIGH) Error indication (ERR) pin to indicate 1-bit error detection and correction The control signal OE is de-asserted Pb-free 36-pin SOJ and 44-pin TSOP II packages On the CY7C1049GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the 1 Functional Description assertion of the ERR output (ERR = HIGH) . See the Truth Table on page 14 for a complete description of read and write CY7C1049G and CY7C1049GE are high-performance CMOS modes. fast static RAM devices with embedded ECC. Both devices are The logic block diagram is on page 2. Product Portfolio Power Dissipation Speed Operating I , CC 3 Features and Options (see Pin V Range (ns) Standby, I (mA) CC SB2 Product Range Configurations on page 4) (V) (mA) f = f 10/15 max 4 4 Typ Max Typ Max CY7C1049G(E)18 Single or Dual Chip Enables Industrial 1.65 V2.2 V 15 40 6 8 CY7C1049G(E)30 2.2 V3.6 V 10 38 45 Optional ERR pins CY7C1049G(E) 4.5 V5.5 V 10 38 45 Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 or details. 3. The ERR pin is available only for devices which have ERR option E in the ordering code. Refer Ordering Information on page 15 for details. 4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V), CC CC V = 3 V (for a V range of 2.2 V3.6 V), and V = 5 V (for a V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-95412 Rev. *F Revised April 3, 2018CY7C1049G CY7C1049GE Logic Block Diagram CY7C1049G DATA IN ECCENCODER DRIVERS A0 A1 A2 A3 512Kx8 I/O I/O 0 7 A4 RAMARRAY A5 A6 A7 A8 A9 COLUMN DECODER WE CE OE Logic Block Diagram CY7C1049GE DATA IN ECCENCODER DRIVERS A0 A1 A2 A3 512Kx8 I/O I/O 0 7 A4 RAMARRAY A5 ERR A6 A7 A8 A9 COLUMN WE CE DECODER OE Document Number: 001-95412 Rev. *F Page 2 of 19 ROWDECODER ROWDECODER A10 A11 A10 A12 A11 A13 A12 A14 A13 A15 A14 A16 A15 A17 A16 A18 A17 A18 SENSE SENSE AMPLIFIERS AMPLIFIERS ECCDECODER ECCDECODER