70V261L25PFG Renesas

HIGH-SPEED 3.3V 70V261S/L 16K x 16 DUAL-PORT STATIC RAM Features IDT70V261 easily expands data bus width to 32 bits or more True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than access of the same memory location one device High-speed access M/S = VIH for BUSY output flag on Master Commercial: 25/35ns (max.) M/S = VIL for BUSY input on Slave Industrial: 25ns (max.) Interrupt Flag Low-power operation On-chip port arbitration logic IDT70V261S Full on-chip hardware support of semaphore signaling Active: 300mW (typ.) between ports Standby: 3.3mW (typ.) Fully asynchronous operation from either port IDT70V261L TTL-compatible, single 3.3V (0.3V) power supply Active: 300mW (typ.) Available in a 100-pin TQFP, Thin Quad Plastic Flatpack Standby: 660W (typ.) Industrial temperature range (-40C to +85C) is available Separate upper-byte and lower-byte control for multiplexed for selected speed bus compatibility Functional Block Diagram R/WL R/WR UBL UBR LBL LBR CEL CER OEL OER I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R (1,2) (1,2) BUSYR BUSYL A13R A13L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 14 14 ARBITRATION INTERRUPT CEL CER SEMAPHORE OER OEL LOGIC R/WL R/WR SEML SEMR (2) (2) INTR INTL M/S 3040 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. 1 Jun.04.2170V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges Description This device provides two independent ports with separate control, The IDT70V261 is a high-speed 16K x 16 Dual-Port Static RAM. The address, and I/O pins that permit independent, asynchronous access for IDT70V261 is designed to be used as a stand-alone 256K-bit Dual-Port reads or writes to any location in memory. An automatic power down RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or- more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. approach in 32-bit or wider memory system applications results in full- Fabricated using CMOS high-performance technology, these de- speed, error-free operation without the need for additional discrete logic. vices typically operate on only 300mW of power. The IDT70V261 is packaged in a 100-pin Thin Quad Flatpack. (1,2,3) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7L 76 50 A6R 49 A7R A8L 77 48 A8R A9L 78 47 A10L 79 A9R A11L 80 46 A10R 81 45 A11R A12L A13L 82 44 A12R LBL 83 43 A13R UBL 42 LBR 84 CEL 85 41 UBR SEML 40 CER 86 70V261 SEMR R/WL 87 39 (4) PNG100 VCC 88 38 GND OEL 89 37 R/WR 36 I/O0L 90 OER I/O1L 91 35 I/O15R GND 92 34 GND 93 I/O2L 33 I/O14R 94 I/O3L 32 I/O13R I/O4L 95 31 I/O12R 96 I/O5L 30 I/O11R I/O6L 97 29 I/O10R I/O7L 98 28 I/O9R 99 I/O8L 27 I/O8R I/O9L 100 26 I/O7R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 3040 drw 02 NOTES: Pin Names 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. Left Port Right Port Names 3. Package body is approximately 14mm x 14mm x 1.4mm. Chip Enable CEL CER 4. This package code is used to reference the package diagram. R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag UBL UBR Upper Byte Select LBL LBR Lower Byte Select BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3040 tbl 01 6.422 Jun.04.21 N/C N/C N/C N/C N/C N/C N/C A6L I/O10L A5L I/O11L A4L A3L I/O12L I/O13L A2L GND A1L I/O14L A0L INTL I/O15L VCC BUSYL GND GND I/O0R M/S BUSYR I/O1R I/O2R INTR VCC A0R A1R I/O3R A2R I/O4R I/O5R A3R A4R I/O6R A5R N/C N/C N/C N/C N/C N/C N/C