HIGH-SPEED 3.3V 70V26S/L 16K x 16 DUAL-PORT STATIC RAM Features IDT70V26 easily expands data bus width to 32 bits or more True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than reads of the same memory location one device High-speed access M/S = VIH for BUSY output flag on Master Commercial: 25/35/55ns (max.) M/S = VIL for BUSY input on Slave Low-power operation On-chip port arbitration logic IDT70V26S Full on-chip hardware support of semaphore signaling Active: 300mW (typ.) between ports Standby: 3.3mW (typ.) Fully asynchronous operation from either port IDT70V26L TTL-compatible, single 3.3V (0.3V) power supply Active: 300mW (typ.) Available in 84-pin PGA and PLCC Standby: 660W (typ.) Green parts available, see ordering information Separate upper-byte and lower-byte control for multiplexed bus compatibility Functional Block Diagram R/WL R/WR UBR UBL LBL LBR CEL CER OEL OER I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0R-I/O7R I/O0L-I/O7L (1,2) (1,2) BUSYL BUSYR A13L A13R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 14 14 ARBITRATION CEL CER SEMAPHORE LOGIC SEML SEMR M/S 2945 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs are non-tri-stated push-pull. JULY 2019 1 DSC 2945/19 2019 Integrated Device Technology, Inc.70V26S/L High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Range Description The IDT70V26 is a high-speed 16K x 16 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down IDT70V26 is designed to be used as a stand-alone 256K-bit Dual-Port feature controlled by CE permits the on-chip circuitry of each port to enter RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or- a very low standby power mode. more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM Fabricated using CMOS high-performance technology, these de- approach in 32-bit or wider memory system applications results in full- vices typically operate on only 300mW of power. speed, error-free operation without the need for additional discrete logic. The IDT70V26 is packaged in a ceramic 84-pin PGA and This device provides two independent ports with separate control, 84-Pin PLCC. address, and I/O pins that permit independent, asynchronous access for (1,2,3) Pin Configurations 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 I/O9R 33 11 I/O7L I/O10R 34 10 I/O6L I/O11R 35 9 I/O5L I/O12R 36 8 I/O4L I/O13R 37 I/O3L 7 I/O14R 38 I/O2L 6 VSS 39 VSS 5 I/O15R 40 I/O 4 1L OER 41 I/O0L 3 R/WR 42 OEL 2 70V26 43 VSS (4) VDD PLG84 1 SEMR 44 R/WL 84 84-Pin PLCC CER 45 Top View 83 SEML 46 UBR CEL 82 LBR 47 81 UBL 48 A13R 80 LBL 49 A12R A13L 79 A11R 50 78 A12L 51 A10R A11L 77 A9R 52 76 A10L A8R 53 75 A9L 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 2945 drw 02 NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 1.15 in x 1.15 in x .17 in. 4. This package code is used to reference the package diagram. 6.42 2 A7R I/O8R A6R I/O7R A5R I/O6R A4R I/O5R A3R I/O4R A2R I/O3R A1R VDD A0R I/O2R BUSYR I/O1R M/S I/O0R VSS VSS BUSYL VDD A0L I/O15L I/O14L A1L A2L VSS A3L I/O13L A4L I/O12L A5L I/O11L I/O10L A6L A7L I/O9L A8L I/O8L