HIGH-SPEED 3.3V IDT70V27S/L 32K x 16 DUAL-PORT STATIC RAM LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features: Dual chip enables allow for depth expansion without True Dual-Ported memory cells which allow simultaneous external logic access of the same memory location IDT70V27 easily expands data bus width to 32 bits or more High-speed access using the Master/Slave select when cascading more than Commercial: 15/20/25/35/55ns (max.) one device Industrial: 15/20/35ns (max.) M/S = VIH for BUSY output flag on Master, Low-power operation M/S = VIL for BUSY input on Slave IDT70V27S Busy and Interrupt Flags Active: 500mW (typ.) Full on-chip hardware support of semaphore signaling Standby: 3.3mW (typ.) between ports IDT70V27L Fully asynchronous operation from either port Active: 500mW (typ.) LVTTL-compatible, single 3.3V (0.3V) power supply Standby: 660W (typ.) Available in 100-pin Thin Quad Flatpack (TQFP) Separate upper-byte and lower-byte control for bus Industrial temperature range (-40C to +85C) is available matching capability for selected speeds On-chip port arbitration logic Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R CE1L CE1R OER OEL LBR LBL I/O8-15L I/O8-15R I/O I/O Control Control I/O0-7L I/O0-7R , (1,2) (1,2) BUSYL BUSYR 32Kx16 A14R A14L Address Address MEMORY Decoder Decoder ARRAY A0L A0R 70V27 A14L A14R A0R A0L ARBITRATION CE0L INTERRUPT CE0R SEMAPHORE CE1L CE1R LOGIC OEL OER R/WL R/WR L SEM SEMR (2) (2) INTL INTR (2) M/S NOTES: 3603 drw 01 1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2) BUSY and INT are non-tri-state totem-pole outputs (push-pull). JANUARY 2019 6.01 1 2019 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC 3603/17IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Description: reads or writes to any location in memory. An automatic power down The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM, feature controlled by the chip enables (CE0 and CE1) permits the on-chip designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a circuitry of each port to enter a very low standby power mode. combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word Fabricated using CMOS high-performance technology, these systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- devices typically operate on only 500mW of power. The IDT70V27 is bit or wider memory system applications results in full-speed, error-free packaged in a 100-pin Thin Quad Flatpack (TQFP). operation without the need for additional discrete logic. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for 2