70V28L20PFG Renesas

70V28L HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master, access of the same memory location M/S = VIL for BUSY input on Slave High-speed access Busy and Interrupt Flags Commercial: 15/20ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT70V28L Fully asynchronous operation from either port Active: 440mW (typ.) Separate upper-byte and lower-byte controls for multi- Standby: 660W (typ.) plexed bus and bus matching compatibility Dual chip enables allow for depth expansion without LVTTL-compatible, single 3.3V (0.3V) power supply external logic Available in a 100-pin TQFP IDT70V28 easily expands data bus width to 32 bits or Industrial temperature range (40C to +85C) is available more using the Master/Slave select when cascading more for selected speeds Green parts available, see ordering information than one device Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R CE1L CE1R OER OEL LBR LBL 8-15L I/O8-15R I/O I/O I/O Control Control 0-7L I/O I/O0-7R (1,2) (1,2) BUSYR BUSYL 64Kx16 15L A15R A Address Address MEMORY Decoder Decoder ARRAY 0L A A0R 70V28 16 16 ARBITRATION CE0R CE0L INTERRUPT SEMAPHORE CE1L CE1R LOGIC OEL OER R/WL R/WR SEML SEMR (2) (2) INTR INTL (1) M/S NOTES: 4849 drw 01 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). JUNE 2019 1 2019 Integrated Device Technology, Inc. DSC-4849/870V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V28 is a high-speed 64K x 16 Dual-Port Static RAM. for reads or writes to any location in memory. An automatic power down The IDT70V28 is designed to be used as a stand-alone 1024K-bit feature controlled by the chip enables (either CE0 or CE1) Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM permit the on-chip circuitry of each port to enter a very low standby for 32-bit-or-more word system. Using the IDT MASTER/SLAVE Dual- power mode. Port RAM approach in 32-bit or wider memory system applications Fabricated using CMOS high-performance technology, these de- results in full-speed, error-free operation without the need for addi- vices typically operate on only 440mW of power. tional discrete logic. The IDT70V28 is packaged in a 100-pin Thin Quad Flatpack This device provides two independent ports with separate control, (TQFP). address, and I/O pins that permit independent, asynchronous access (1,2,3) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 NC A8R 76 A7R 49 I/O9R 77 48 A6R 78 I/O8R A5R 47 I/O7R 79 46 A4R 80 Vcc 45 I/O6R A3R 81 A2R 44 82 I/O5R A1R I/O4R 83 43 A0R 42 I/O3R 84 INTR 41 I/O2R 85 70V28 40 I/O1R BUSYR 86 (4) 39 I/O0R M/S 87 PNG100 GND 88 38 GND BUSYL 89 37 I/O0L 100-Pin TQFP 36 INTL 90 I/O1L Top View NC 91 35 GND A0L 92 34 I/O2L 93 33 A1L I/O3L A2L 94 I/O4L 32 A3L 95 31 I/O5L A4L 96 30 I/O6L A5L 29 I/O7L 97 A6L 98 28 Vcc A7L 99 27 I/O8L 100 A8L 26 I/O9L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4849 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 A9L A9R A10R A10L A11L A11R A12L A12R A13L A13R A14L A14R A15L A15R NC NC NC NC LBL LBR UBL UBR CE0L CE0R CE1L CE1R SEML SEMR Vcc GND R/WL R/WR OEL OER GND GND GND GND I/O15L I/O15R I/O14L I/O14R I/O13L I/O13R I/O12L I/O12R I/O11L I/O11R I/O10L I/O10R