HIGH-SPEED 3.3V 70V3319/99S 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: True Dual-Port memory cells which allow simultaneous Self-timed write allows fast cycle time access of the same memory location Separate byte controls for multiplexed bus and bus High-speed data access matching compatibility Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Dual Cycle Deselect (DCD) for Pipelined Output mode Industrial: 4.2ns (133MHz) (max.) LVTTL- compatible, single 3.3V (150mV) power supply Selectable Pipelined or Flow-Through output mode for core Due to limited pin count PL/FT option is not supported LVTTL compatible, selectable 3.3V (150mV) or 2.5V on the 128-pin TQFP package. Device is pipelined (100mV) power supply for I/Os and control signals on outputs only on each port. each port Counter enable and repeat features Industrial temperature range (-40C to +85C) is Dual chip enables allow for depth expansion without available at 133MHz. additional logic Available in a 128-pin Thin Quad Flatpack, 208-pin fine Full synchronous operation on both ports pitch Ball Grid Array, and 256-pin Ball 6ns cycle time, 166MHz operation (6Gbps bandwidth) Grid Array Fast 3.6ns clock to data out Supports JTAG features compliant to IEEE 1149.1 1.7ns setup to clock and 0.5ns hold on all control, data, and Due to limited pin count, JTAG is not supported on the address inputs 166MHz 128-pin TQFP package Data input, address, byte enable and control registers Green parts available, see ordering information Functional Block Diagram UBL UBR LBL LBR FT/PIPEL 1b 0b 1a 0a 0a 1a 0b 1b FT/PIPER 1/0 1/0 ab b a R/WL R/WR CE0L CE0R 1 1 CE1L CE1R B B B B 0 0 W W W W 0 1 1 0 1/0 L L R R 1/0 Dout0-8 L Dout0-8 R OEL OER Dout9-17 L Dout9-17 R , 0a 1a 1b 0b 1a 0a 0b 1b 0/1 FT/PIPEL 0/1 FT/PIPER ab ba 256K x 18 MEMORY ARRAY Din L I/O0R - I/O17R I/O0L - I/O17L Din R , CLKR CLKL (1) (1) A17L A17R Counter/ A0L Counter/ A 0R ADDR R ADDR L Address REPEATL Address REPEATR ADSR ADSL Reg. Reg. CNTENL CNTENR 5623 tbl 01 TDI TCK NOTE: TMS JTAG TDO TRST 1. A17 is a NC for IDT70V3399. NOVEMBER 2019 1 DSC 5623/13 2019 Integrated Device Technology, Inc.70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous or bidirectional data flow in bursts. An automatic power down feature, Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlled by CE0 and CE1, permits the on-chip circuitry of each port to allow simultaneous access of any address from both ports. Registers on enter a very low standby power mode. control, data, and address inputs provide minimal setup and hold The 70V3319/99 can support an operating voltage of either 3.3V or times. The timing latitude provided by this approach allows systems 2.5V on one or both ports, controllable by the OPT pins. The power supply to be designed with very short cycle times. With an input data register, the for the core of the device (VDD) remains at 3.3V. IDT70V3319/99 has been optimized for applications having unidirectional (1,2,3,4,5) Pin Configuration 112 3 4 5 6 7 8 9 101 12 13 14 15 16 17 I/O9L NC VSS NC A16L A12L A8L NC VDD A0L OPTL NC VSS A TDO CLKL CNTEN L A4L NC VSS NC (1) A9L TDI A17L A13L NC CE0L VSS ADSL VSS VDDQR I/O8L NC B A5L A1L I/O9R VDDQR PIPE/FTL NC A14L VDDQL A10L UBL CE1L VSS A6L A2L VDD I/O8R NC VSS C R/WL NC VSS I/O10L VDD NC VDDQL I/O7R NC A15L A11L A7L LBL OEL REPEAT L A3L VDD I/O7L D I/O11L NC VDDQR I/O10R I/O6L NC VSS NC E VDDQL I/O11R VSS I/O6R NC VDDQR NC VSS F NC VSS I/O12L NC NC 70V3319/99 VDDQL I/O5L NC G (6) BF208 (6) VDD VSS NC VDDQR I/O12R NC I/O5R H VDD BFG208 VDDQL VDD VSS VDD VSS VDDQR VSS VSS J 208-Pin fpBGA I/O3R I/O14R VSS I/O13R VSS VDDQL I/O4R VSS K (7) Top View NC I/O14L VDDQR I/O13L I/O4L NC I/O3L VSS L VDDQL NC I/O15R VSS VSS NC I/O2R VDDQR M NC VSS NC I/O15L I/O1R VDDQL NC I/O2L N I/O16R I/O16L VDDQR TRST A16R A8R NC NC A12R NC VDD CLKR CNTEN R A4R NC I/O1L VSS P (1) TCK A17R A13R VSS NC I/O17R A9R NC CE0R VSS ADSR A5R VSS VDDQL I/O0R VDDQR R A1R VSS NC NC I/O17L VDDQL TMS NC A14R A10R UBR CE1R VSS R/WR A6R A2R VSS NC T VSS NC PIPE/FTR A7R LBR VDD OER REPEAT R A3R VDD NC I/O0L NC A15R A11R A0R OPTR U 5623 drw 02c NOTES: 1. A17 is a NC for IDT70V3399. 2. All VDD pins must be connected to 3.3V power supply. 3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 4. All VSS pins must be connected to ground supply. 5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 6.422