HIGH-SPEED 3.3V 256K x 18 70V631S ASYNCHRONOUS DUAL-PORT STATIC RAM Features Fully asynchronous operation from either port True Dual-Port memory cells which allow simultaneous Separate byte controls for multiplexed bus and bus access of the same memory location matching compatibility High-speed access Supports JTAG features compliant to IEEE 1149.1 Commercial: 10/12/15ns (max.) Due to limited pin count, JTAG is not supported on the Industrial: 12ns (max.) 128-pin TQFP package. Dual chip enables allow for depth expansion without LVTTL-compatible, single 3.3V (150mV) power supply for external logic core IDT70V631 easily expands data bus width to 36 bits or LVTTL-compatible, selectable 3.3V (150mV)/2.5V (100mV) more using the Master/Slave select when cascading more power supply for I/Os and control signals on each port than one device Available in a 128-pin Thin Quad Flatpack, 208-ball fine M/S = VIH for BUSY output flag on Master, pitch Ball Grid Array, and 256-ball Ball Grid Array M/S = VIL for BUSY input on Slave Industrial temperature range (40C to +85C) is available Busy and Interrupt Flags for selected speeds On-chip port arbitration logic Green parts available, see ordering information Full on-chip hardware support of semaphore signaling between ports Functional Block Diagram UBL UBR LBL LBR R/WL R/WR B B B B E E E E 0 1 1 0 CE0L CE0R L L R R CE1L CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R 256K x 18 MEMORY ARRAY Din L I/O0L-I/O17L Din R I/O0R - I/O17R A17R Address Address A17L ADDR L ADDR R Decoder Decoder A0R A0L OEL ARBITRATION OER INTERRUPT CE0R CE0L SEMAPHORE CE1R CE1L LOGIC R/WL R/WR BUSYL BUSYR SEML M/S SEMR INTL INTR TMS TDI JTAG TCK TDO TRST 5622 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). SEPTEMBER 2019 1 2019 Integrated Device Technology, Inc. DSC-5622/970V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V631 is a high-speed 256K x 18 Asynchronous Dual-Port address, and I/O pins that permit independent, asynchronous access for Static RAM. The IDT70V631 is designed to be used as a stand-alone reads or writes to any location in memory. An automatic power down 4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual- feature controlled by the chip enables (either CE0 or CE1) permit the Port RAM for 36-bit-or-more word system. Using the IDT MASTER/ on-chip circuitry of each port to enter a very low standby power mode. SLAVE Dual-Port RAM approach in 36-bit or wider memory system The 70V631 can support an operating voltage of either 3.3V or 2.5V applications results in full-speed, error-free operation without the need for on one or both ports, controlled by the OPT pins. The power supply for additional discrete logic. the core of the device (VDD) remains at 3.3V. This device provides two independent ports with separate control, (1,2,3,4) Pin Configurations 1 2 3 4 5 6 7 8 9 11 12 13 14 10 15 16 17 I/O9L A12L VDD NC VSS TDO A16L A8L NC A4L A0L OPTL NC VSS A NC SEML INTL A NC VSS NC A9L TDI A17L A13L NC CE0L VSS A5L A1L VSS VDDQR I/O8L NC B BUSYL B I/O9R VDD NC A14L A10L CE1L VSS A2L VDD I/O8R VSS VDDQL VDDQR UBL A6L NC C R/WL C NC VSS I/O10L NC A15L A11L A7L VDD NC VDD VDDQL I/O7L I/O7R LBL OEL A3L NC D D I/O11L VDDQR I/O10R NC I/O6L NC VSS NC E E VDDQL I/O11R VSS I/O6R VDDQR NC VSS NC F F NC VSS I/O12L NC VDDQL I/O5L NC NC G G 70V631 VDD (5) NC VDDQR I/O12R VDD NC VSS I/O5R H H BF208 (5) BFG208 VDDQL VDD VSS VDD VSS VDDQR VSS VSS J J 208-Ball BGA VDDQL I/O3R I/O4R VSS I/O14R VSS I/O13R VSS K K (6) Top View NC I/O14L VDDQR I/O13L NC I/O3L VSS I/O4L L L VDDQL NC I/O15R VSS VSS NC I/O2R VDDQR M M NC VSS NC I/O15L I/O1R VDDQL NC I/O2L N N I/O16R I/O16L VDDQR VDD A4R NC I/O1L NC NC TRST A16R A12R A8R NC INTR VSS P SEMR P A13R A9R NC VSS A5R A1R VSS VDDQL I/O0R VDDQR R VSS NC I/O17R TCK A17R CE0R R BUSYR VSS VSS A14R A10R VSS A6R A2R NC NC NC I/O17L VDDQL TMS NC UBR CE1R R/WR T T VDD OPTR NC I/O0L VSS A11R A7R VDD A3R A0R NC VDD NC A15R LBR OER M/S U U 5622 tbl 02b NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V) and 2.5V if OPT pin for that port is IL (0V). set to V 3. All VSS pins must be connected to ground. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 2