HIGH-SPEED 70121L 2K x 9 DUAL-PORT 70125L STATIC RAM WITH BUSY & INTERRUPT Features High-speed access Fully asychronous operation from either port On-chip port arbitration logic (IDT70121 only) Commercial: 25ns (max.) Low-power operation BUSY output flag on Master BUSY input on Slave IDT70121/70125L INT flag for port-to-port communication Active: 675mW (typ.) Battery backup operation2V data retention TTL-compatible, signal 5V (10%) power supply Standby: 1mW (typ.) MASTER IDT70121 easily expands data bus width to 18 bits or Available in 52-pin PLCC Green parts available, see ordering information more using SLAVE IDT70125 chip Functional Block Diagram OER OEL CER CEL R/WR R/WL I/O0L- I/O8L I/O0R-I/O8R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A10R A10L Address MEMORY Address Decoder ARRAY Decoder A0R A0L 11 11 ARBITRATION CEL CER INTERRUPT OER OEL LOGIC R/WR R/WL (2) (2) INTL INTR 2654 drw 01 NOTES: 1. 70121 (MASTER): BUSY is non-tri-stated push-pull output. 70125 (SLAVE): BUSY is input. 2. INT is non-tri-stated push-pull output. SEPTEMBER 2019 1 DSC 2654/15 2019 Integrated Device Technology, Inc.70121L/70125L High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Range Description feature, controlled by CE, permits the on-chip circuitry of each port to enter The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static a very low standby power mode. RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual- The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for Port RAM or as a MASTER Dual-Port RAM together with the IDT70125 Data/Control and parity bits at the users option. This feature is especially SLAVE Dual-Port in 18-bit-or-more word width systems. Using the IDT useful in data communications applications where it is necessary to use a MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory parity bit for transmission/reception error checking. system applications results in full-speed, error-free operation without the Fabricated using CMOS high-performance technology, these need for additional discrete logic. devices typically operate on only 675mW of power. Low-power (L) Both devices provide two independent ports with separate control, versions offer battery backup data retention capability with each port address, and I/O pins that permit independent, asynchronous access for typically consuming 200W from a 2V battery. reads or writes to any location in memory. An automatic power-down The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC. (1,2,3) Pin Configurations 09/16/19 7 I/O4L 21 A0L 22 I/O5L 6 OEL 5 A10L I/O6L 23 24 4 I/O7L INTL I/O8L 25 3 BUSYL GND 26 2 R/WL 70121/125 27 I/O0R 1 (4) CEL PLG52 I/O1R 28 52 VCC CER I/O2R 29 52-Pin PLCC 51 I/O3R 30 Top View R/WR 50 I/O4R 31 49 BUSYR I/O5R 32 48 INTR I/O6R 33 A10R 47 2654 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 2 6.42 34 20 I/O3L I/O7R 35 I/O8R 19 I/O2L 36 18 I/O1L A9R 37 A8R 17 I/O0L A7R 38 16 A9L 39 A6R 15 A8L A5R 40 14 A7L 41 A4R 13 A6L A3R 42 12 A5L 43 A A2R 11 4L A1R 44 10 A3L A0R 45 A2L 9 46 OER 8 A1L