HIGH-SPEED IDT7024S/L
4K x 16 DUAL-PORT
STATIC RAM
IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
True Dual-Ported memory cells which allow simultaneous
one device
reads of the same memory location
M/S = H for BUSY output flag on Master
High-speed access
M/S = L for BUSY input on Slave
Military: 20/25/35/55/70ns (max.)
Interrupt Flag
Industrial: 55ns (max.)
On-chip port arbitration logic
Commercial: 15/17/20/25/35/55ns (max.)
Full on-chip hardware support of semaphore signaling
Low-power operation
between ports
IDT7024S
Fully asynchronous operation from either port
Active: 750mW (typ.)
Battery backup operation2V data retention
Standby: 5mW (typ.)
TTL-compatible, single 5V (10%) power supply
IDT7024L
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Active: 750mW (typ.)
Quad Flatpack
Standby: 1mW (typ.)
Industrial temperature range (40C to +85C) is available
Separate upper-byte and lower-byte control for multiplexed
for selected speeds
bus compatibility
R/ R/
L R
R
L
L
R
R
L
R
L
I/O8L-I/O15L I/O8R-I/O15R
I/O I/O
Control Control
I/O0L-I/O7L I/O0R-I/O7R
(1,2)
(1,2)
L R
A11R
A11L
Address MEMORY Address
Decoder ARRAY Decoder
A0L
A0R
12
12
ARBITRATION
R
L INTERRUPT
R
L SEMAPHORE
LOGIC R
R/L R/
R
L
(2)
(2)
M/
R
L
2740 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
1
DSC 2740/10
2000 Integrated Device Technology, Inc.
This datasheet has been downloaded from IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The port to enter a very low standby power mode.
Fabricated using IDTs CMOS high-performance technology, these
IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
devices typically operate on only 750mW of power. Low-power (L)
or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach versions offer battery backup data retention capability with typical power
in 32-bit or wider memory system applications results in full-speed, error- consumption of 500W from a 2V battery.
free operation without the need for additional discrete logic. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack
and PLCC, and a 100-pin TQFP. Military grade product is manufactured
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for in compliance with the latest revision of MIL-PRF-38535 QML, making it
reads or writes to any location in memory. An automatic power down ideally suited to military temperature applications demanding the highest
feature controlled by chip enable (CE) permits the on-chip circuitry of each level of performance and reliability.
!
INDEX
1110 98 7654 32 18483 82 81 80 79 78 77 76 75
I/O8L 74 A7L
12
A6L
I/O9L 73
13
5L
I/O10L A
14 72
A4L
I/O11L 71
15
A3L
I/O12L
16 70
A2L
I/O13L 69
17
A1L
GND
68
18
IDT7024J or F
A0L
I/O14L 67
19
(4)
J84-1
L
I/O15L
(4) 66
20 F84-2
VCC L
21 65
84-Pin PLCC / Flatpack
GND GND
64
22 (5)
Top View
I/O0R
23 63 M/
I/O1R
62
24 R
I/O2R
25 61
R
VCC 60
26 A0R
I/O3R
27 59 1R
A
I/O4R 58
28 A2R
I/O5R
29 57 A3R
I/O6R 56 4R
30 A
I/O7R
31 55 A5R
I/O8R 54 A6R
32
Index
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
,
2740 drw 02
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N/C 1 75
N/C
2
N/C 74 N/C
N/C 3 73
N/C
4 72
N/C N/C
I/O10L 5 71 A5L
I/O11L 6 70 4L
A
I/O12L 7 69
A3L
68
I/O13L 8 A2L
GND 9 67 A1L
I/O14L 10 66
A0L
IDT7024PF
11 65
I/O15L
L
(4)
PN100-1
VCC 12 64
L
GND 13 63
GND
100-Pin TQFP
62
I/O0R 14 M/
(5)
Top View
61
I/O1R 15 R
60
I/O2R 16
R
CC 17 59
V A0R
58
I/O3R 18 A1R
I/O4R 19 57
A2R
5R 20 56
I/O A3R
55
I/O6R 21 A4R
NOTES:
54
N/C 22
N/C
1. All VCC pins must be connected to the power supply. 53
N/C 23 N/C
52
N/C 24 N/C
2. All GND pins must be connected to the ground supply.
51
N/C 25
N/C
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.
2740 drw 03
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
I/O9R
I/O7L
10R
I/O
I/O6L
I/O11R
I/O5L
I/O12R
4L
I/O
I/O13R
I/O3L
14R
I/O
I/O2L
GND
GND
15R
I/O
I/O1L
R
I/O0L
R/R
L
GND
VCC
R
L
R/
R
L
R
L
R
L
N/C
L
11R
A
N/C
A10R
A11L
A9R
10L
A
A8R
A9L
7R
A 8L
A
9L
I/O7R I/O
I/O8R I/O8L
I/O9R I/O7L
6L
I/O10R I/O
I/O11R I/O5L
I/O12R I/O4L
3L
I/O13R I/O
I/O14R I/O2L
GND
GND
1L
I/O15R I/O
I/O0L
R
R/R
L
GND VCC
R R/L
L
R
R L
R L
L
N/C
A11R N/C
R A11L
A10
A10L
A9R
A8R A9L
7R A8L
A
A6R A7L
A5R A6L