HIGH-SPEED 7026S/L 16K X 16 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous IDT7026 easily expands data bus width to 32 bits or more access of the same memory location using the Master/Slave select when cascading more than High-speed access one device Commercial: 15/20/25/35ns (max.) M/S = H for BUSY output flag on Master, Industrial: 20ns (max.) M/S = L for BUSY input on Slave Military: 25/35ns (max.) On-chip port arbitration logic Low-power operation Full on-chip hardware support of semaphore signaling IDT7026S between ports Active: 750mW (typ.) Fully asynchronous operation from either port Standby: 5mW (typ.) TTL-compatible, single 5V (10%) power supply IDT7026L Available in 84-pin PGA and 84-pin PLCC Active: 750mW (typ.) Industrial temperature range (-40C to +85C) is available Standby: 1mW (typ.) for selected speeds Separate upper-byte and lower-byte control for multi- Green parts available, see ordering information plexed bus compatibility Functional Block Diagram R/WL R/WR UBL UBR LBL LBR CEL CER OEL OER I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R (1,2) (1,2) BUSYR BUSYL A13R A13L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 14 14 ARBITRATION CEL CER SEMAPHORE LOGIC SEMR SEML M/S 2939 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs are non-tri-stated push-pull. AUGUST 2019 1 DSC 2939/177026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description feature controlled by CE permits the on-chip circuitry of each port to enter The IDT7026 is a high-speed 16K x 16 Dual-Port Static RAM. The a very low standby power mode. IDT7026 is designed to be used as a stand-alone Dual-Port RAM or as Fabricated using CMOS high-performance technology, these de- a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word vices typically operate on only 750mW of power. systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- The IDT7026 is packaged in a ceramic 84-pin PGA, and a 84-pin bit or wider memory system applications results in full-speed, error-free PLCC. Military grade product is manufactured in compliance with MIL- operation without the need for additional discrete logic. PRF-38535 QML, making it ideally suited to military temperature appli- This device provides two independent ports with separate control, cations demanding the highest level of performance and reliability. address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down (1,2,3) Pin Configurations 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 I/O9R 33 11 I/O7L 34 I/O10R 10 I/O6L 35 I/O11R 9 I/O5L I/O12R 36 8 I/O4L 37 I/O13R 7 I/O3L I/O14R 38 6 I/O2L GND 39 GND 5 I/O15R 40 4 I/O1L OER 41 I/O0L 3 IDT7026 R/WR 42 (4) OEL 2 PLG84 GND 43 1 VCC SEMR 44 84-Pin PLCC 84 R/WL Top View CER 45 83 SEML UBR 46 CEL 82 LBR 47 81 UBL A13R 48 80 LBL A12R 49 79 A13L A11R 50 78 A12L A10R 51 77 A11L A9R 52 A10L 76 A8R 53 75 A9L 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 2939 drw 02 NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 1.15 in x 1.15 in x .17 in. 4. This package code is used to reference the package diagram. 6.42 2 A7R I/O8R A6R I/O7R A5R I/O6R I/O5R A4R A3R I/O4R A2R I/O3R A1R VCC A0R I/O2R BUSYR I/O1R I/O0R M/S GND GND BUSYL VCC I/O15L A0L A1L I/O14L A2L GND I/O13L A3L A4L I/O12L I/O11L A5L I/O10L A6L A7L I/O9L A8L I/O8L