7027S/L HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM Features IDT7027 easily expands data bus width to 32 bits or more True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than access of the same memory location High-speed access one device M/S = VIH for BUSY output flag on Master, Commercial: 15/25/35/55ns (max.) M/S = VIL for BUSY input on Slave Industrial: 20ns (max.) Busy and Interrupt Flags Low-power operation IDT7027S On-chip port arbitration logic Full on-chip hardware support of semaphore signaling Active: 750mW (typ.) between ports Standby: 5mW (typ.) Fully asynchronous operation from either port IDT7027L TTL-compatible, single 5V (10%) power supply Active: 750mW (typ.) Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin Standby: 1mW (typ.) Ceramic Pin Grid Array (PGA) Separate upper-byte and lower-byte control for bus Industrial temperature range (40C to +85C) is available matching capability. for selected speeds Dual chip enables allow for depth expansion without external logic Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R CE1L CE1R OER OEL LBR LBL 8-15L I/O8-15R I/O I/O I/O Control Control 0-7L I/O I/O0-7R (1,2) BUSYR BUSYL . 32Kx16 A14L A14R Address Address MEMORY Decoder Decoder ARRAY A0L A0R 7027 A14L A14R A0R A0L ARBITRATION CE0L CE0R INTERRUPT SEMAPHORE CE1L CE1R LOGIC OEL OER R/WL R/WR SEML SEMR (2) (2) INTR INTL (2) M/S NOTES: 3199 drw 01 1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). JUNE 2019 1 DSC 3199/127027S/L High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description address, and I/O pins that permit independent, asynchronous access for The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM, reads or writes to any location in memory. An automatic power down designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode. combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word Fabricated using CMOS high-performance technology, these de- systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- bit or wider memory system applications results in full-speed, error-free vices typically operate on only 750mW of power. The IDT7027 is operation without the need for additional discrete logic. packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic The device provides two independent ports with separate control, Pin Grid Array (PGA). (1,2,3) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A8R 76 50 NC A7R 49 I/O9R 77 48 A6R I/O8R 78 A5R 47 I/O7R 79 A4R 46 80 Vcc 45 A3R 81 I/O6R 44 A2R 82 I/O5R A1R 83 43 I/O4R A0R 84 42 I/O3R INTR 85 41 I/O2R BUSYR 86 40 I/O1R 7027 M/S 87 39 I/O0R (4 ) PNG100 GND 88 38 GND BUSYL 89 37 100-Pin I/O0L 90 TQFP 36 INTL I/O1L Top View 91 35 NC GND 92 34 A0L I/O2L 93 33 A1L I/O3L 94 A2L 32 I/O4L A3L 95 31 I/O5L A4L 96 30 I/O6L 97 29 A5L I/O7L 98 28 A6L Vcc A7L 27 I/O8L 99 26 I/O9L A8L 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 3199 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram 2 6.42 A9L A9R A10R A10L A11R A11L A12R A12L A13L A13R A14L A14R NC NC NC NC NC NC LBL LBR UBL UBR CE0L CE0R CE1L CE1R SEML SEMR Vcc GND R/WL R/WR OEL OER GND GND GND GND I/O15L I/O15R I/O14L I/O14R I/O13L I/O13R I/O12L I/O12R I/O11L I/O11R I/O10L I/O10R