GS8673ET18/36BK-675/625/550/500 675 MHz500 MHz 260-Ball BGA 72Mb SigmaDDR-IIIe 1.35 V V Commercial Temp DD Burst of 2 ECCRAM Industrial Temp 1.2 V to 1.5 V V DDQ Features Clocking and Addressing Schemes On-Chip ECC with virtually zero SER The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are Configurable Read Latency (3.0 or 2.0 cycles) synchronous devices. They employ dual, single-ended master Simultaneous Read and Write SigmaDDR-IIIe Interface clocks, CK and CK. These clocks are single-ended clock Common I/O Bus inputs, not differential inputs to a single differential clock input Double Data Rate interface buffer. CK and CK are used to control the address and control Burst of 2 Read and Write input registers, as well as all output timing. Pipelined read operation Fully coherent Read and Write pipelines The KD and KD clocks are dual mesochronous (with respect to 1.35 V nominal V CK and CK) input clocks that are used solely to control the DD data input registers. Consequently, data input setup and hold 1.2 V JESD8-16A BIC-3 Compliant Interface windows can be optimized independently of address and 1.5 V HSTL Interface control input setup and hold windows. ZQ pin for programmable output drive impedance ZT for programmable input termination impedance Each internal read and write operation in a SigmaDDR-IIIe B2 Configurable Input Termination ECCRAM is two times wider than the device I/O bus. An input IEEE 1149.1 JTAG-compliant Boundary Scan data bus de-multiplexer is used to accumulate incoming data 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package before it is simultaneously written to the memory array. An K: 5/6 RoHS-compliant package output data multiplexer is used to capture the data produced GK: 6/6 RoHS-compliant package from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address SigmaDDR-IIIe Family Overview field of a SigmaDDR-IIIe B2 ECCRAM is always one address The SigmaDDR-IIIe family of SRAMs are the Common I/O pin less than the advertised index depth (e.g. the 4M x 18 has half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high 2M addressable index). performance SRAMs. Although very similar to GSI s second generation of networking SRAMs, the SigmaQuad-II/ On-Chip Error Correction Code SigmaDDR-II family, this third generation family of SRAMs GSI s ECCRAMs implement an ECC algorithm that detects offers new features that allow much higher speeds, such as and corrects all single-bit memory errors, including those user-configurable on-die input termination, improved output induced by Soft Error Rate (SER) events such as cosmic rays, signal integrity, and adjustable pipeline length. alpha particles, etc. The resulting SER of these devices is anticipated to be <0.002 FITs/Mb a 5-order-of-magnitude improvement over comparable SRAMs with no On-Chip ECC, which typically have an SER of 200 FITs/Mb or more. SER quoted above is based on reading taken at sea level. Parameter Synopsis V Speed Bin Operating Frequency Data Rate (per pin) Read Latency DD -675 675 / 450 MHz 1350 / 900 Mbps 3.0 / 2.0 1.3V to 1.4V -625 625 / 400 MHz 1250 / 800 Mbps 3.0 / 2.0 1.3V to 1.4V -550 550 / 375 MHz 1100 / 750 Mbps 3.0 / 2.0 1.25V to 1.4V -500 500 / 333 MHz 1000 / 666 Mbps 3.0 / 2.0 1.25V to 1.4V Rev: 1.06 12/2017 1/37 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8673ET18/36BK-675/625/550/500 4M x 18 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 MCH V V V V MCL MCL ZQ PZT1 V V V V A DD DDQ DD DDQ DDQ DD DDQ DD (CFG) NC MCL V NU V NU NU V V MVQ MCL PZT0 DQ0 B SS IO SS I I SS SS (RSVD) (SIOM) DQ17 V NU V V SA V SA V V NU V NU C DDQ I DDQ SS DD SS DDQ I DDQ IO NC NC V NU V NU V V NU V V SA DQ1 D SS IO SS I DDQ DDQ I SS SS (288 Mb) (144 Mb) V DQ16 V NU V V SA SA V V NU V NU E SS DDQ I DD SS SS DD I DDQ IO V NU V NU SA V V V SA NU V DQ2 V F SS IO SS I DD DDQ DD I SS SS NU NU NU V V NU NU NU DQ15 SA MZT1 SA DQ3 G IO I I SS SS I I IO DQ14 V NU V SA V R/W V SA V NU V NU H DDQ I DDQ DDQ DDQ DDQ I DDQ IO V NU V NU V V V NU V V SA SA DQ4 J SS IO SS I SS SS SS I SS SS CQ1 V V V KD1 V CK V KD0 V V V CQ0 K DDQ REF DD DD DD DD REF DDQ CQ1 V QVLD1 V KD1 V CK V KD0 V QVLD0 V CQ0 L SS SS DDQ DDQ SS SS V V NU V V V NU V NU V DQ13 SA SA M SS SS I SS SS SS I SS IO SS NU V NU V DLL V LD V MCH V NU V DQ5 N IO DDQ I DDQ DDQ DDQ DDQ I DDQ NU NU NU V V NU NU NU DQ12 SA MZT0 SA DQ6 P IO I I SS SS I I IO V DQ11 V NU MCH V V V RST NU V NU V R SS SS I DD DDQ DD I SS IO SS NU V NU V V SA V SA V V NU V DQ7 T IO DDQ I DD SS SS SS DD I DDQ V V NU NU V V NU NU V NU V DQ10 AZT1 U SS SS I I DDQ DDQ I I SS IO SS SA SA NU V NU V V V V V NU V DQ8 V IO DDQ I DDQ SS DD SS DDQ I DDQ (x18) (B2) NC V V NU NU V NU V DQ9 TCK RLM0 MCL TMS W SS SS I I SS IO SS (RSVD) V V V V TDO ZT RLM1 MCL TDI V V V V Y DD DDQ DD DDQ DDQ DD DDQ DD Notes: 1. Pins 5A, 7A, and 6B are reserved for future use. They must be tied Low. 2. Pins 9N and 5R are reserved for future use. They must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration. 4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration. 5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device. 6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device. 7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device. 8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device. 9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low. 10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low. 11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device. Rev: 1.06 12/2017 2/37 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see