GS81280Z18/36GT-xxxV 333 MHz200 MHz 100-Pin TQFP 144Mb Pipelined and Flow Through 1.8 V or 2.5 V V Commercial Temp DD Synchronous NBT SRAM Industrial Temp 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the NBT (No Bus Turn Around) functionality allows zero wait input clock. Burst order control (LBO) must be tied to a power read-write-read bus utilization Fully pin-compatible with rail for proper operation. Asynchronous inputs include the both pipelined and flow through NtRAM, NoBL and Sleep mode enable (ZZ) and Output Enable. Output Enable can ZBT SRAMs be used to override the synchronous control of the output 1.8 V or 2.5 V +10%/10% core power supply drivers and turn the RAM s output drivers off at any time. 1.8 V or 2.5 V I/O supply Write cycles are internally self-timed and initiated by the rising User-configurable Pipeline and Flow Through mode edge of the clock input. This feature eliminates complex off- LBO pin for Linear or Interleave Burst mode chip write pulse generation required by asynchronous SRAMs Pin compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb and simplifies input signal timing. devices Byte write operation (9-bit Bytes) The GS81280Z18/36GT-xxxV may be configured by the user 3 chip enable signals for easy depth expansion to operate in Pipeline or Flow Through mode. Operating as a ZZ Pin for automatic power-down pipelined synchronous device, meaning that in addition to the RoHS-compliant 100-lead TQFP package available rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For Functional Description read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle The GS81280Z18/36GT-xxxV is a 144Mbit Synchronous and then released to the output drivers at the next rising edge of Static SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL clock. or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus The GS81280Z18/36GT-xxxV is implemented with GSI s high bandwidth by eliminating the need to insert deselect cycles performance CMOS technology and is available in a JEDEC- when the device is switched from read to write cycles. standard 100-pin TQFP package. Parameter Synopsis -333 -250 -200 Unit t 2.5 2.5 3.0 ns KQ 3.0 4.0 5.0 ns Pipeline tCycle 3-1-1-1 Curr (x18) 530 430 360 mA Curr (x32/x36) 580 460 390 mA t 4.5 5.5 6.5 ns KQ 4.5 5.5 6.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 400 360 285 mA Curr (x32/x36) 420 380 320 mA Rev: 1.01a 8/2017 1/21 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS81280Z18/36GT-xxxV GS81280Z18GT Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 8M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.01a 8/2017 2/21 2015, GSI Technology Specifications cited are subject to change without notice. For latest documentation see