GS8160F18/32/36DGT-6.5/7.5 6.5 ns 7.5 ns 100-Pin TQFP 1M x 18, 512K x 32, 512K x 36 2.5 V or 3.3 V V Commercial Temp DD 18Mb Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O positive-edge-triggered clock input (CK). Output enable (G) Features and power down control (ZZ) are asynchronous inputs. Burst Flow Through mode operation cycles can be initiated with either ADSP or ADSC inputs. In Single Cycle Deselect (SCD) operation Burst mode, subsequent burst addresses are generated 2.5 V or 3.3 V +10%/10% core power supply internally and are controlled by ADV. The burst address 2.5 V or 3.3 V I/O supply counter may be configured to count in either linear or LBO pin for Linear or Interleaved Burst mode interleave order with the Linear Burst Order (LBO) input. The Internal input resistors on mode pins allow floating mode pins Burst function need not be used. New addresses can be loaded Byte Write (BW) and/or Global Write (GW) operation on every cycle with no degradation of chip performance. Internal self-timed write cycle Automatic power-down for portable applications Byte Write and Global Write RoHS-compliant 100-lead TQFP package available Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for Functional Description writing all bytes at one time, regardless of the Byte Write Applications control inputs. The GS8160F18/32/36DGT is an 18,874,368-bit high Sleep Mode performance synchronous SRAM with a 2-bit burst address Low power (Sleep mode) is attained through the assertion counter. Although of a type originally developed for Level 2 (High) of the ZZ signal, or by stopping the clock (CK). Cache applications supporting high performance CPUs, the Memory data is retained during Sleep mode. device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip Core and Interface Voltages set support. The GS8160F18/32/36DGT operates on a 3.3 V or 2.5 V power supply. All input are 3.3 V and 2.5 V compatible. Controls Separate output power (V ) pins are used to decouple Addresses, data I/Os, chip enables (E1, E2, E3), address burst DDQ control inputs (ADSP, ADSC, ADV), and write control inputs output noise from the internal circuits and are 3.3 V and 2.5 V (Bx, BW, GW) are synchronous and are controlled by a compatible. Parameter Synopsis -6.5 -7.5 Unit t 6.5 7.5 ns KQ 6.5 7.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 205 190 mA Curr (x32/x36) 225 205 mA Rev: 1.01 10/2013 1/22 2013, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8160F18/32/36DGT-6.5/7.5 GS8160F18D 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 1M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 67 NC SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.01 10/2013 2/22 2013, GSI Technology Specifications cited are subject to change without notice. For latest documentation see