HIGH-SPEED 7028L 64K x 16 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master, reads of the same memory location M/S = VIL for BUSY input on Slave Interrupt Flag High-speed access Commercial: 15ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports Fully asynchronous operation from either port IDT7028L Active: 1W (typ.) Separate upper-byte and lower-byte controls for multi- Standby: 1mW (typ.) plexed bus and bus matching compatibility Dual chip enables allow for depth expansion without TTL-compatible, single 5V (10%) power supply external logic Available in a 100-pin TQFP Industrial temperature range (40C to +85C) is available IDT7028 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more for selected speeds than one device Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R CE1L CE1R OER OEL LBR LBL 8-15L I/O8-15R I/O I/O I/O Control Control 0-7L I/O I/O0-7R (1,2) (1,2) BUSY BUSYR L 64Kx16 A15L A15R Address Address MEMORY Decoder Decoder ARRAY A0L A0R 7028 16 16 ARBITRATION CE0L CE0R INTERRUPT SEMAPHORE CE1L CE1R LOGIC OEL OER R/WL R/WR SEML SEMR (2) (2) INTR INTL (2) M/S NOTES: 4836 drw 01 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). JUNE 2019 1 DSC-4836/67028L High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT7028 is a high-speed 64K x 16 Dual-Port Static RAM. The address, and I/O pins that permit independent, asynchronous access for IDT7028 is designed to be used as a stand-alone 1024K-bit Dual-Port reads or writes to any location in memory. An automatic power down RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or- feature controlled by the chip enables (CE0 and CE1) permit the on-chip more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM circuitry of each port to enter a very low standby power mode. approach in 32-bit or wider memory system applications results in full- Fabricated using CMOS high-performance technology, these de- speed, error-free operation without the need for additional discrete logic. vices typically operate on only 1W of power. This device provides two independent ports with separate control, The IDT7028 is packaged in a 100-pin Thin Quad Flatpack (TQFP). (1,2,3) Pin Configurations 63 74 73 72 71 70 69 68 67 66 65 64 62 61 60 59 58 57 56 55 54 53 52 51 75 A8R 50 NC 76 A7R 49 I/O9R 77 A6R 48 I/O8R 78 A5R 47 79 I/O7R A4R 46 80 Vcc A3R 45 81 I/O6R A2R 44 82 I/O5R A1R 83 43 I/O4R A0R 42 84 I/O3R INTR 41 I/O2R 85 BUSYR 40 I/O1R 86 7028 M/S 87 39 I/O0R (4) PNG100 GND 88 38 GND BUSYL 89 37 I/O0L INTL 90 36 I/O1L 100-Pin TQFP NC 91 Top View GND 35 A0L 34 92 I/O2L A1L 93 33 I/O3L A2L 94 32 I/O4L A3L 95 31 I/O5L A4L 96 30 I/O6L A5L 97 29 I/O7L A6L 98 Vcc 28 A7L 99 27 I/O8L A8L 100 I/O9L 26 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 4836 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 A9L A9R A10R A10L A11R A11L A12R A12L A13L A13R A14L A14R A15L A15R NC NC NC NC LBL LBR UBL UBR CE0L CE0R CE1L CE1R SEML SEMR Vcc GND R/WL R/WR OEL OER GND GND GND GND I/O15L I/O15R I/O14L I/O14R I/O13L I/O13R I/O12L I/O12R I/O11L I/O11R I/O10L I/O10R