7038L HIGH-SPEED 64K x 18 DUAL-PORT STATIC RAM Features M/S = VIH for BUSY output flag on Master, True Dual-Ported memory cells which allow simultaneous M/S = VIL for BUSY input on Slave reads of the same memory location Interrupt Flag High-speed access On-chip port arbitration logic Commercial: 15ns (max.) Full on-chip hardware support of semaphore signaling Industrial: 20ns (max.) between ports Low-power operation Fully asynchronous operation from either port IDT7038L Separate upper-byte and lower-byte controls for multi- Active: 1W (typ.) plexed bus and bus matching compatibility Standby: 1mW (typ.) TTL-compatible, single 5V (10%) power supply Dual chip enables allow for depth expansion without Available in a 100-pin TQFP external logic Industrial temperature range (40C to +85C) is available IDT7038 easily expands data bus width to 36 bits or for selected speeds more using the Master/Slave select when cascading more Green parts available, see ordering information than one device Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R CE1L CE1R OER OEL LBR LBL I/O 9-17L I/O9-17R I/O I/O Control Control I/O 0-8L I/O0-8R (1,2) (1,2) BUSYR BUSYL . 64Kx18 A15L A15R Address Address MEMORY Decoder Decoder ARRAY A0L A0R 7038 16 16 ARBITRATION CE0R CE0L INTERRUPT SEMAPHORE CE1L CE1R LOGIC OEL OER R/WL R/WR SEML SEMR (2) (2) INTR INTL (1) M/S 4837 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). JUNE 2019 1 DSC-4837/77038L High-Speed 64K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT7038 is a high-speed 64K x 18 Dual-Port Static RAM. The address, and I/O pins that permit independent, asynchronous access for IDT7038 is designed to be used as a stand-alone 1152K-bit Dual-Port reads or writes to any location in memory. An automatic power down RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or- feature controlled by the chip enables (CE0 and CE1) permit the on-chip more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM circuitry of each port to enter a very low standby power mode. approach in 36-bit or wider memory system applications results in full- Fabricated using CMOS high-performance technology, these de- speed, error-free operation without the need for additional discrete logic. vices typically operate on only1W of power. This device provides two independent ports with separate control, The IDT7038 is packaged in a 100-pin Thin Quad Flatpack (TQFP). (1,2,3) Pin Configurations over 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7R I/O10R 76 50 A6R I/O9R 77 49 I/O8R A5R 78 48 47 I/O7R A4R 79 46 Vcc A3R 80 I/O6R A2R 81 45 I/O5R A1R 82 44 I/O4R A0R 83 43 INTR 84 42 I/O3R I/O2R BUSYR 85 41 7038 40 I/O1R M/S 86 (4) 87 PNG100 39 I/O0R VCC GND GND 88 38 GND 89 37 I/O0L 100-Pin TQFP I/O1L BUSYL 90 36 Top View GND INTL 91 35 92 I/O2L A0L 34 93 I/O3L A1L 33 94 32 I/O4L A2L 95 31 I/O5L A3L I/O6L A4L 96 30 I/O7L A5L 97 29 Vcc A6L 98 28 I/O8L A7L 99 27 A8L I/O9L 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4837 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 A9L A8R A10L A9R A10R A11L A11R A12L A12R A13L A14L A13R A15L A14R A15R LBL LBR UBL UBR CE0L CE1L CE0R CE1R SEML R/WL SEMR R/WR OEL Vcc GND GND OER GND I/O17L I/O16L I/O17R GND GND I/O15L I/O16R I/O14L I/O15R I/O13L I/O14R I/O12L I/O13R I/O11L I/O12R I/O10L I/O11R