HIGH-SPEED 64/32K x 8 709089/79S/L SYNCHRONOUS OBSOLETE PARTS DUAL-PORT STATIC RAM LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features: True Dual-Ported memory cells which allow simultaneous Dual chip enables allow for depth expansion without access of the same memory location additional logic High-speed clock to data access Full synchronous operation on both ports Commercial: 9/12/15ns (max.) 4ns setup to clock and 1ns hold on all control, data, Industrial: 12ns (max.) and address inputs Low-power operation Data input, address, and control registers IDT709089/79S Fast 9ns clock to data out in the Pipelined output mode Active: 950mW (typ.) Self-timed write allows fast cycle time Standby: 5mW (typ.) 15ns cycle time, 66.7MHz operation in the Pipelined IDT709089/79L output mode Active: 950mW (typ.) TTL- compatible, single 5V (10%) power supply Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Flow-Through or Pipelined output mode on either port via for selected speeds the FT/PIPE pin Available in 100-pin Thin Quad Flatpack (TQFP) package Counter enable and reset features Green parts available, see ordering information Functional Block Diagram R/WR R/WL OEL OER CE0R CE0L 1 1 CE1L CE1R 0 0 0/1 0/1 1 0 0 1 FT/PIPEL 0/1 0/1 FT/PIPER I/O0L - I/O7L I/O0R - I/O7R I/O I/O Control Control (1) (1) A15L A15R Counter/ Counter/ A0R MEMORY A0L Address Address CLKR CLKL ARRAY Reg. Reg. ADSR ADSL CNTENR CNTENL CNTRSTR CNTRSTL . 3242 drw 01 NOTE: 1. A15X is a NC for IDT709079. JANUARY 2018 1 DSC-3242/17 2018 Integrated Device Technology, Inc. OBSOLETE PARTS NOT RECOMMENDED FOR NEW DESIGNS709089/79S/L High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: With an input data register, the IDT709089/79 has been optimized for The IDT709089/79 is a high-speed 64/32K x 8 bit synchronous Dual- applications having unidirectional or bidirectional data flow in bursts. Port RAM. The memory array utilizes Dual-Port memory cells to allow An automatic power down feature, controlled by CE0 and CE1, permits simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these latitude provided by this approach allows systems to be designed with very devices typically operate on only 950mW of power. short cycle times. (1,2,3) Pin Configuration NC 76 50 NC NC 77 49 NC A6R 78 48 NC 79 A5R 47 I/O7R A4R 80 46 I/O6R 81 A3R 45 I/O5R A2R 82 44 I/O4R A1R 83 43 I/O3R 84 A0R 42 VCC 85 CNTENR 41 I/O2R 86 CLKR 40 I/O1R ADSR 87 39 I/O0R (5) 709089/79 88 GND 38 GND PN100 89 ADSL 37 VCC CLKL 90 36 I/O0L 91 CNTENL 35 I/O1L A0L 92 34 GND A1L 93 33 I/O2L A2L 94 32 I/O3L 95 A3L 31 I/O4L A4L 96 30 I/O5L 97 A5L 29 I/O6L 98 A6L 28 I/O7L NC 99 27 NC NC 100 26 GND 3242 drw 02 Index NOTES: 1. A15X is a NC for IDT709079. 2. All VCC pins must be connected to power supply. 3. All GND pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6.422 NC 1 NC 75 NC 2 74 NC A7L 3 73 A7R 4 A8R A8L 72 A9L 5 71 A9R A10R A10L 6 70 A11R A11L 7 69 A12L 8 68 A12R A13L 9 67 A13R A14R A14L 66 10 65 A15R A15L 11 NC 64 NC 12 GND VCC 63 13 62 NC NC 14 NC 61 NC 15 NC 16 60 NC 59 NC NC 17 CE0L 58 CE0R 18 CE1R CE1L 19 57 56 20 CNTRSTR CNTRSTL 55 R/WR R/WL 21 OEL 54 OER 22 53 FT/PIPER FT/PIPEL 23 52 GND NC 24 25 51 NC NC