HIGH-SPEED 64K x 16 IDT709289L SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features True Dual-Ported memory cells which allow simultaneous Full synchronous operation on both ports access of the same memory location 4ns setup to clock and 0ns hold on all control, data, and High-speed clock to data access address inputs Commercial: 7.5/9/12ns (max.) Data input, address, and control registers Industrial: 9ns (max.) Fast 7.5ns clock to data out in the Pipelined output mode Low-power operation Self-timed write allows fast cycle time IDT709289L 12ns cycle time, 83MHz operation in Pipelined output mode Active: 1.2W (typ.) Separate upper-byte and lower-byte controls for Standby: 2.5mW (typ.) multiplexed bus and bus matching compatibility Flow-Through or Pipelined output mode on either Port via TTL- compatible, single 5V (10%) power supply the FT/PIPE pins Industrial temperature range (40C to +85C) is Counter enable and reset features available for selected speeds Dual chip enables allow for depth expansion without Available in a 100-pin Thin Quad Flatpack (TQFP) package additional logic Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R 1 1 CE1L CE1R 0 0 0/1 0/1 LBL LBR OEL OER 1b 0b 1a 0a 0a 1a 0b 1b FT/PIPEL 0/1 ba ab 0/1 FT/PIPER I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R A15R A15L Counter/ Counter/ MEMORY A0R A0L Address Address CLKR CLKL ARRAY Reg. Reg. ADSR ADSL CNTENR CNTENL CNTRSTL CNTRSTR 4842 drw 01 FEBRUARY 2018 1 DSC-4842/8 2018 Integrated Device Technology, Inc.IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT709289 is a high-speed 64K x 16 bit synchronous Dual- With an input data register, the IDT709289 has been optimized for applications having unidirectional or bidirectional data flow in bursts. Port RAM. The memory array utilizes Dual-Port memory cells to allow An automatic power down feature, controlled by CE0 and CE1, permits simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold the on-chip circuitry of each port to enter a very low standby power times. The timing latitude provided by this approach allows systems mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 1.2W of power. to be designed with very short cycle times. (1,2,3) Pin Configurations Index 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9R 1 A9L 75 A10R 2 74 A10L A11R 3 73 A11L A12R 4 72 A12L A13R 5 71 A13L A14R 6 70 A14L A15R 7 69 A15L 68 NC 8 NC 9 67 NC NC 10 66 LBR LBL IDT709289PF 11 65 UBR UBL (4) PN100 64 CE0R 12 CE0L 63 CE1R 13 CE1L 100-Pin TQFP . 62 CNTRSTR CNTRSTL 14 (5) Top View 15 61 GND Vcc 60 16 R/WR R/WL 59 OEL 17 OER 58 FT/PIPEL 18 FT/PIPER 57 GND 19 GND 56 I/O15L 20 I/O15R 55 I/O14L 21 I/O14R 54 I/O13L 22 I/O13R 53 I/O12L 23 I/O12R 52 I/O11L 24 I/O11R 51 I/O10L 25 I/O10R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 4842 drw 02a NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.422 A8L I/O9L A7L I/O8L A6L Vcc A5L I/O7L A4L I/O6L A3L I/O5L A2L I/O4L A1L I/O3L A0L I/O2L CNTENL GND CLKL I/OIL ADSL I/O0L GND GND ADSR I/O0R I/O1R CLKR CNTENR I/O2R A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R Vcc I/O7R A5R I/O8R A6R I/O9R A7R NC A8R