HIGH-SPEED 2.5V 70T3509M 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: Data input, address, byte enable and control registers Self-timed write allows fast cycle time True Dual-Port memory cells which allow simultaneous access of the same memory location Separate byte controls for multiplexed bus and bus High-speed data access matching compatibility Dual Cycle Deselect (DCD) for Pipelined Output Mode Commercial: 4.2ns (133MHz)(max.) 2.5V (100mV) power supply for core Industrial: 4.2ns (133MHz)(max.) Selectable Pipelined or Flow-Through output mode LVTTL compatible, selectable 3.3V (150mV) or 2.5V Counter enable and repeat features (100mV) power supply for I/Os and control signals on each port Interrupt Flags Includes JTAG functionality Full synchronous operation on both ports 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth) Available in a 256-pin Ball Grid Array (BGA) 1.5ns setup to clock and 0.5ns hold on all control, data, and Common BGA footprint provides design flexibility over seven density generations (512K to 36M-bit) address inputs 133MHz Green parts available, see ordering information Fast 4.2ns clock to data out Functional Block Diagram BE3R BE3L BE2L BE2R BE1L BE1R BE0L BE0R FT/PIPEL 0a 1a 0b 1b 0c 1c 0d 1d 1d 0d 1c 0c 1b 0b 1a 0a FT/PIPER 1/0 1/0 ab c d dc b a R/WL R/WR (2) (2) CE0L CE0R 1 1 CE1L CE1R 0 0 B B B B B B B B 1/0 1/0 W W W W W W W W 0 1 2 3 3 2 1 0 L L L L R R R R OER OEL Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R , 1d 0d 1c 0c 1b 0b 1a 0a 0a 1a 0b 1b 0c 1c 0d 1d 0/1 0/1 FT/PIPER FT/PIPEL abcd dcb a 1024K x 36 MEMORY ARRAY I/O0L - I/O35L I/O0R - I/O35R Din L Din R , CLKL CLKR A19L A19R Counter/ A0L Counter/ A0R ADDR R ADDR L REPEATL Address Address REPEATR ADSR ADSL Reg. Reg. CNTENL CNTENR TDI TCK CE0 CE 0 R TMS L INTERRUPT JTAG CE1 R TRST CE1L LOGIC TDO R/WL R/W R INTL INTR (1) ZZ (1) ZZL ZZR CONTROL 5682 drw 01 LOGIC NOTES: 1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 2. See Truth Table I for Functionality. OCTOBER 2019 1 DSC 5682/1270T3509M High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70T3509M is a high-speed 1024K x 36 bit synchronous or bidirectional data flow in bursts. An automatic power down feature, Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlled by CE0 and CE1, permits the on-chip circuitry of each port to allow simultaneous access of any address from both ports. Registers on enter a very low standby power mode. control, data, and address inputs provide minimal setup and hold times. The 70T3509M can support an operating voltage of either 3.3V or The timing latitude provided by this approach allows systems to be 2.5V on one or both ports, controllable by the OPT pins. The power supply designed with very short cycle times. With an input data register, the for the core of the device (VDD) is at 2.5V. IDT70T3509M has been optimized for applications having unidirectional 6.422