CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture 36-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports CY7C1425KV18 4M 9 Supports concurrent transactions CY7C1412KV18 2M 18 333 MHz clock for high bandwidth CY7C1414KV18 1M 36 Two-word burst on all accesses Functional Description Double data rate (DDR) Interfaces on both read and write ports The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 (data transferred at 666 MHz) at 333 MHz are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: Two input clocks (K and K) for precise DDR timing the read port and the write port to access the memory array. The SRAM uses rising edges only read port has dedicated data outputs to support read operations Two input clocks for output data (C and C) to minimize clock and the write port has dedicated data inputs to support write skew and flight time mismatches operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the Echo clocks (CQ and CQ) simplify data capture in high speed data bus that exists with common I/O devices. Access to each systems port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input Single multiplexed address input bus latches address inputs (K) clock. Accesses to the QDR II read and write ports are for both read and write ports completely independent of one another. To maximize data Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 9-bit Synchronous internally self-timed writes words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or QDR II operates with 1.5 cycle read latency when DOFF is 36-bit words (CY7C1414KV18) that burst sequentially into or out asserted HIGH of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and Operates similar to QDR I device with 1 cycle read latency when C and C), memory bandwidth is maximized while simplifying DOFF is asserted LOW system design by eliminating bus turnarounds. Available in 9, 18, and 36 configurations Depth expansion is accomplished with port selects, which enables each port to operate independently. Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by Core V = 1.8 V (0.1 V) I/O V = 1.4 V to V DD DDQ DD the K or K input clocks. All data outputs pass through output Supports both 1.5 V and 1.8 V I/O supply registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip Available in 165-ball FBGA package (13 15 1.4 mm) synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free Packages For a complete list of related documentation, click here. Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement Selection Guide Description 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 333 300 250 MHz Maximum operating current 9 730 680 590 mA 18 750 700 610 36 910 850 730 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-57825 Rev. *O Revised January 3, 20182M x 9 Array 1M x 18 Array 2M x 9 Array 1M x 18 Array CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 Logic Block Diagram CY7C1425KV18 9 D 8:0 Write Write 21 Address A Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 18 V 9 REF 9 CQ Reg. Reg. Control WPS Logic 9 9 BWS Q Reg. 0 8:0 9 Logic Block Diagram CY7C1412KV18 18 D 17:0 Write Write 20 Address A Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 36 V 18 REF 18 CQ Reg. Reg. Control WPS Logic 18 18 BWS Q Reg. 1:0 17:0 18 Document Number: 001-57825 Rev. *O Page 2 of 33 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode