HIGH-SPEED 2.5V 70T3519/99/89S 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: Data input, address, byte enable and control registers True Dual-Port memory cells which allow simultaneous Self-timed write allows fast cycle time Interrupt and Collision Detection Flags access of the same memory location Separate byte controls for multiplexed bus and bus High-speed data access matching compatibility Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ Dual Cycle Deselect (DCD) for Pipelined Output Mode 4.2ns (133MHz)(max.) 2.5V (100mV) power supply for core Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) LVTTL compatible, selectable 3.3V (150mV) or 2.5V Selectable Pipelined or Flow-Through output mode (100mV) power supply for I/Os and control signals on Counter enable and repeat features each port Dual chip enables allow for depth expansion without Industrial temperature range (-40C to +85C) is additional logic available at 166MHz and 133MHz Full synchronous operation on both ports Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine 5ns cycle time, 200MHz operation (14Gbps bandwidth) pitch Ball Grid Array (fpBGA) Fast 3.4ns clock to data out Supports JTAG features compliant with IEEE 1149.1 1.5ns setup to clock and 0.5ns hold on all control, data, and Green parts available, see ordering information address inputs 200MHz Functional Block Diagram BE3R BE3L BE2L BE2R BE1L BE1R BE0L BE0R FT/PIPEL 0a 1a 0b 1b 0c 1c 0d 1d 1d 0d 1c 0c 1b 0b 1a 0a FT/PIPER 1/0 1/0 dc b a ab c d R/WL R/WR CE0L CE0R 1 1 CE1R CE1L 0 0 B B B B B B B B 1/0 1/0 W W W W W W W W 0 1 2 3 3 2 1 0 L L L L R R R R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R Dout18-26 L Dout18-26 R Dout27-35 L Dout27-35 R , 1d 0d 1c 0c 1b 0b 1a 0a 0a 1a 0b 1b 0c 1c 0d 1d FT/PIPEL 0/1 0/1 FT/PIPER abcd dcba 256/128/64K x 36 MEMORY ARRAY I/O0L-I/O35L Din L I/O0R - I/O35R Din R , CLKR CLKL (1) (1) A17R A17L Counter/ A0L Counter/ A0R ADDR R ADDR L REPEATL Address REPEATR Address ADSR ADSL Reg. Reg. CNTENL CNTENR TDI TCK INTERRUPT CE0 CE 0 R TMS L JTAG COLLISION CE1 R TRST CE1L TDO DETECTION R/WL R/W LOGIC R COL L COLR INTL INTR (2) (2) ZZ ZZL ZZR CONTROL 5666 drw 01 LOGIC NOTES: 1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC s for the IDT70T3589. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx NOVEMBER 2019 and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 1 DSC 5666/14 2019 Integrated Device Technology, Inc.70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70T3519/99/89 is a high-speed 256/128/64K x 36 bit tional or bidirectional data flow in bursts. An automatic power down feature, synchronous Dual-Port RAM. The memory array utilizes Dual-Port controlled by CE0 and CE1, permits the on-chip circuitry of each port to memory cells to allow simultaneous access of any address from both ports. enter a very low standby power mode. Registers on control, data, and address inputs provide minimal setup and The 70T3519/99/89 can support an operating voltage of either 3.3V hold times. The timing latitude provided by this approach allows systems or 2.5V on one or both ports, controllable by the OPT pins. The power to be designed with very short cycle times. With an input data register, the supply for the core of the device (VDD) is at 2.5V. IDT70T3519/99/89 has been optimized for applications having unidirec- 6.422