70P249L65BYGI Renesas

IDT70P269/259/249L VERY LOW POWER 1.8V 16K/8K/4K X 16 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous Power supply isolation functionality to aid system power reads of the same memory location management Both ports configurable to standard SRAM or time- Separate upper-byte and lower-byte control multiplexed address/data interface Input Read Register High-speed access Output Drive Register Industrial: 65ns (max.), ADM mode BUSY and Interrupt Flag Industrial: 40ns (max.), Standard SRAM mode On-chip port arbitration logic Low-power operation Fully asynchronous operation from either port IDT70P269/259/249L Available in 100 Ball 0.5mm-pitch BGA Active: 27mW (typ.) Industrial temperature range (-40C to +85C) Standby: 3.6W (typ.) Green parts available, see ordering information Supports 3.0V, 2.5V and 1.8V I/O s Functional Block Diagram (2) IRR1 IRR0 SFEN IRR/ODR ODR4 ODR0 I/O I/O I/O I/O 15L 8L 15R 8R Data <15..0> Data <15..0> I/O7L I/O0L I/O7R I/O0R Muxed Muxed Address / Memory Array Address / Data 16K/8K/4K x 16 Data ADV ADV L R I/O Control I/O Control AddrR <13..0> AddrR <13..0> UBL UBR LB LB L R A A A A 13L 0L 13R 0R Address Address MSELL MSELR Decode Decode CS CS L R OE Control Logic OE L R WE WE L R BUSY BUSY L R INT INT L R 7146 drw 01 NOTES: 1. A13 - A0 for IDT70P269 A12 - A0 for IDT70P259 A11 - A0 for IDT70P249. 2. IRR0 and IRR1 are not available for IDT70P269. OCTOBER 2008 1 DSC-7146/1 2008 Integrated Device Technology, Inc.IDT70P269/259/249L Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range DescriptionDescription DescriptionDescriptionDescription Fabricated using IDTs CMOS high-performance technology, these The IDT70P269/259/249 is a very low power 16K/8K/4K x 16 Dual- devices typically operate on only 27mW of power. Port Static RAM. The IDT70P269/259/249 is designed to be used as a The IDT70P269/259/249 is packaged in a 100 ball 0.5mm- pitch Ball stand-alone 256/128/64K-bit Dual-Port SRAM. Grid Array. The package is a 1mm thick and designed to fit in wireless This device provides two independent ports with separate control, handset applications. address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port to enter a very low standby power mode. (2,3) Pin Configurations 70P269/259/249BY BYG-100 100-Ball 0.5mm Pitch BGA Top View 1234 5 6789 10 A A A UB V ADV I/O I/O I/O V A 5R 8R 11R R SS R 15R 12R 10R SS A A A A A CS WE OE V I/O I/O B 3R 4R 7R 9R R R R DDIOR 9R 6R B (1) A A A A LB IRR I/O I/O I/O V C 0R 1R 2R 6R R 1 14R 11R 7R SS C (3) ODR ODR BUSY INT A A I/O I/O I/O I/O D 4 2 R R 10R 12R 13R 8R 5R 2R D V DNU ODR INT V V I/O V I/O V SS 3 L SS SS 4R DDIOR 1R SS E E SFEN ODR BUSY A V V I/O I/O I/O V 1 L 1L DD SS 3R 0R 15L DDIOL F F (3) ODR A A A OE I/O I/O I/O I/O I/O G 0 2L 5L 12L L 3L 11L 12L 14L 13L G A A A LB CS I/O V MSEL MSEL I/O H 0L 4L 9L L L 1L DDIOL R L 10L H (2) A A A IRR V V I/O I/O I/O I/O J 3L 7L 10L 0 DD SS 4L 6L 8L 9L J A A A UB ADV WE I/O I/O I/O I/O 6L 8L 11L L L L 0L 2L 5L 7L K K 1234 5 6789 10 7146 drw 02 NOTES:- 1. This pin is A13R for IDT70P269. 2. This pin is A13L for IDT70P269. 3. This pin is DNU for IDT70P249. 4. DNU pins aredo not us. No trace or power component can be connected to these pins. 6.422 OCTOBER 16, 2008