70V09L HIGH-SPEED 3.3V 128K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master, access of the same memory location M/S = VIL for BUSY input on Slave High-speed access Busy and Interrupt Flags Commercial: 15ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT70V09L Fully asynchronous operation from either port Active: 440mW (typ.) LVTTL-compatible, single 3.3V (0.3V) power supply Standby: 660W (typ.) Available in a 100-pin TQFP Dual chip enables allow for depth expansion without Industrial temperature range (40C to +85C) is available external logic for selected speeds IDT70V09 easily expands data bus width to 16 bits or Green parts available, see ordering information more using the Master/Slave select when cascading more than one device Functional Block Diagram R/W L R/W R CE0L CE0R CE1L CE1R OE OER L I/O I/O I/O 0-7L I/O 0-7R Control Control (1,2) (1,2) BUSYL BUSYR 128Kx8 A16L A16R MEMORY Address Address ARRAY Decoder Decoder A0L 0R A 70V09 17 17 ARBITRATION CE 0L INTERRUPT CE 0R SEMAPHORE CE 1L CE 1R LOGIC OEL OE R R/WL R/WR SEML SEMR (2) (2) INTL R (1) INT M/S 4852 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). JUNE 2019 1 2019 Integrated Device Technology, Inc. DSC-4852/870V09L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V09 is a high-speed 128K x 8 Dual-Port Static RAM. The reads and writes to any location in memory. An automatic power down IDT70V09 is designed to be used as a stand-alone 1024K-bit Dual-Port feature controlled by the chip enables (either CE0 or CE1) permit the on- RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit- chip circuitry of each port to enter a very low standby power mode. or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM Fabricated using CMOS high-performance technology, these de- approach in 16-bit or wider memory system applications results in full- vices typically operate on only 440mW of power. The IDT70V09 is speed, error-free operation without the need for additional discrete logic. packaged in a 100-pin Thin Quad Flatpack (TQFP). This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for (1,2,3) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC 50 76 NC 49 NC 77 A6R 48 NC 78 A5R 47 I/O7R 79 A4R 46 80 I/O6R 45 A3R 81 I/O5R A2R 82 44 I/O4R A1R 43 I/O3R 83 A0R 42 Vcc 84 INTR 41 85 I/O2R 70V09 BUSYR 40 I/O1R 86 (4) PNG100 39 I/O0R M/S 87 GND GND 88 38 100-Pin Vcc BUSYL 89 37 TQFP INTL 90 Top View 36 I/O0L 91 35 I/O1L NC A0L 34 92 GND A1L I/O2L 93 33 A2L I/O3L 94 32 A3L I/O4L 95 31 A4L 96 I/O5L 30 A5L 97 I/O6L 29 A6L 98 I/O7L 28 NC 99 NC 27 GND NC 100 26 2 3 4 5 6 7 8 9 10111213141516171819202122232425 1 4852 drw NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 NC NC NC NC A7L A7R A8L A8R A9L A9R A10L A10R A11L A11R A12L A12R A13L A13R A14L A14R A15L A15R A16L A16R Vcc GND NC NC NC NC NC NC NC NC CE0L CE0R CE1L CE1R SEML SEMR R/WL R/WR OEL OER GND GND NC GND NC NC