128K X 36, 3.3V Synchronous 71V547S SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs Features Single R/W (READ/WRITE) control pin 128K x 36 memory configuration, flow-through outputs 4-word burst capability (Interleaved or linear) Supports high performance system speed - 95 MHz Individual byte write (BW1 - BW4) control (May tie active) (8ns Clock-to-Data Access) TM Three chip enables for simple depth expansion ZBT Feature - No dead cycles between write and read Single 3.3V power supply (5%) cycles Packaged in a JEDEC standard 100-pin TQFP package Internally synchronized signal eliminates the need to control OE Functional Block Diagram 128K x 36 BIT LBO MEMORY ARRAY Address A 0:16 D Q Address CE1, CE2, CE2 R/W D Q Control CEN ADV/LD DI DO BWx D Q Control Logic Clk Mux Sel Clock Gate OE , Data I/O 0:31 , I/O P 1:4 3822 drw 01 ZBT and Zero Bus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc. 1 Apr.24.20 Input Register71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges There are three chip enable pins (CE1, CE2, CE2) that allow the user Description to deselect the device when desired. If any one of these three is not active The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) when ADV/LD is low, no new memory operation can be initiated and any synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate burst in progress is stopped. However, any pending data transfers (reads dead bus cycles when turning the bus around between reads and writes, or writes) will be completed. The data bus will tri-state one cycle after the TM or writes and reads. Thus it has been given the name ZBT , or Zero Bus chip was deselected or write initiated. Turn-around. The IDT71V547 has an on-chip burst counter. In the burst mode, the Address and control signals are applied to the SRAM during one clock IDT71V547 can provide four cycles of data for a single address presented cycle, and on the next clock cycle, its associated data cycle occurs, be it to the SRAM. The order of the burst sequence is defined by the LBO input read or write. pin. The LBO pin selects between linear and interleaved burst sequence. The IDT71V547 contains address, data-in and control signal regis- The ADV/LD signal is used to load a new external address (ADV/LD = ters. The outputs are flow-through (no output data register). Output enable LOW) or increment the internal burst counter (ADV/LD = HIGH). is the only asynchronous signal and can be used to disable the outputs at The IDT71V547 SRAM utilizes a high-performance, high-volume any given time. 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x A Clock Enable (CEN) pin allows operation of the IDT71V547 to 20mm 100-pin thin plastic quad flatpack (TQFP) for high board density. be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. Pin Description Summary A0 - A16 Address Inputs Input Synchronous CE1, CE2, CE2 Three Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous Clock Enable Input Synchronous CEN Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A ADV/LD Advance Burst Address / Load New Address Input Synchronous Linear / Interleaved Burst Order Input Static LBO I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output I/O Synchronous VDD 3.3V Power Supply Static VSS Ground Supply Static 3822 tbl 01 2 Apr.24.20