GS864218/36/72(B/C)-xxxV 119- & 209-Pin BGA 250 MHz167 MHz 4M x 18, 2M x 36, 1M x 72 Commercial Temp 1.8 V or 2.5 V V DD 72Mb S/DCD Sync Burst SRAMs Industrial Temp 1.8 V or 2.5 V I/O Flow Through/Pipeline Reads Features The function of the Data Output register can be controlled by the FT pin for user-configurable flow through or pipeline operation user via the FT mode . Holding the FT mode pin low places the Single/Dual Cycle Deselect selectable RAM in Flow Through mode, causing output data to bypass the IEEE 1149.1 JTAG-compatible Boundary Scan Data Output Register. Holding FT high places the RAM in ZQ mode pin for user-selectable high/low output drive Pipeline mode, activating the rising-edge-triggered Data Output 1.8 V or 2.5 V core power supply Register. 1.8 V or 2.5 V I/O supply LBO pin for Linear or Interleaved Burst mode SCD and DCD Pipelined Reads Internal input resistors on mode pins allow floating mode pins The GS864218/36/72(B/C)-xxxV is a SCD (Single Cycle Default to SCD x18/x36 Interleaved Pipeline mode Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous Byte Write (BW) and/or Global Write (GW) operation SRAM. DCD SRAMs pipeline disable commands to the same Internal self-timed write cycle degree as read commands. SCD SRAMs pipeline deselect Automatic power-down for portable applications commands one stage less than read commands. SCD RAMs begin JEDEC-standard 119- and 209-bump BGA package turning off their outputs immediately after the deselect command RoHS-compliant 119- and 209-bump BGA packages available has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off Functional Description their outputs just after the second rising edge of clock. The user Applications may configure this SRAM for either mode of operation using the The GS864218/36/72(B/C)-xxxV is a 75,497,472-bit high SCD mode input. performance synchronous SRAM with a 2-bit burst address Byte Write and Global Write counter. Although of a type originally developed for Level 2 Byte write operation is performed by using Byte Write enable Cache applications supporting high performance CPUs, the device (BW) input combined with one or more individual byte write now finds application in synchronous SRAM applications, ranging signals (Bx). In addition, Global Write (GW) is available for from DSP main store to networking chip set support. writing all bytes at one time, regardless of the Byte Write control Controls inputs. Addresses, data I/Os, chip enable (E1), address burst control FLXDrive inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, The ZQ pin allows selection between high drive strength (ZQ low) GW) are synchronous and are controlled by a positive-edge- for multi-drop bus applications and normal drive strength (ZQ triggered clock input (CK). Output enable (G) and power down floating or high) point-to-point applications. See the Output Driver control (ZZ) are asynchronous inputs. Burst cycles can be initiated Characteristics chart for details. with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by Core and Interface Voltages ADV. The burst address counter may be configured to count in The GS864218/36/72(B/C)-xxxV operates on a 1.8 V or 2.5 V either linear or interleave order with the Linear Burst Order (LBO) power supply. All inputs are 1.8 V or 2.5 V compatible. Separate input. The Burst function need not be used. New addresses can be output power (V ) pins are used to decouple output noise from DDQ loaded on every cycle with no degradation of chip performance. the internal circuits and are 1.8 V or 2.5 V compatible. Parameter Synopsis -250 -200 -167 Unit t ) 3.0 3.0 3.4 ns KQ 4.0 5.0 6.0 ns tCycle Pipeline Curr (x18) 340 290 260 mA 3-1-1-1 Curr (x36) 410 350 305 mA Curr (x72) 520 435 380 mA t 6.5 7.5 8.0 ns KQ tCycle 6.5 7.5 8.0 ns Flow Through Curr (x18) 245 220 210 mA 2-1-1-1 Curr (x36) 280 250 240 mA Curr (x72) 370 315 300 mA Rev: 1.05a 2/2009 1/35 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS864218/36/72(B/C)-xxxV 209-Bump BGAx72 Common I/OTop View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB A B DQG DQG BC BG NC BW A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C V V D DQG DQG NC NC G GW NC DQB DQB D SS SS V V V V V V V E DQPG DQPC DQPF DQPB E DDQ DDQ DD DD DD DDQ DDQ V V V V V V F DQC DQC ZQ DQF DQF F SS SS SS SS SS SS V V V V V V G DQC DQC MCH DQF DQF G DDQ DDQ DD DD DDQ DDQ V V V V V V H DQC DQC MCL DQF DQF H SS SS SS SS SS SS V V V V V V J DQC DQC MCL DQF DQF J DDQ DDQ DD DD DDQ DDQ V V K NC NC CK NC MCL NC NC NC NC K SS SS V V V V V V L DQH DQH FT DQA DQA L DDQ DDQ DD DD DDQ DDQ V V V V V V M DQH DQH MCL DQA DQA M SS SS SS SS SS SS V V V V V V N DQH DQH SCD DQA DQA N DDQ DDQ DD DD DDQ DDQ V V V V V V P DQH DQH ZZ DQA DQA P SS SS SS SS SS SS V V V V V V V R DQPD DQPH DQPA DQPE R DDQ DDQ DD DD DD DDQ DDQ V V T DQD DQD NC NC LBO NC NC DQE DQE T SS SS U DQD DQD A A A A A A A DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W 2 11 x 19 Bump BGA14 x 22 mm Body1 mm Bump Pitch Rev: 1.05a 2/2009 2/35 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see