Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1020CV26 512-Kbit (32 K 16) Static RAM 512-Kbit (32 K 16) Static RAM Writing to the device is accomplished by taking chip enable (CE) Features and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O through I/O ), is written into Temperature range 1 8 the location specified on the address pins (A through A ). If 0 14 Automotive: 40 C to 125 C byte high enable (BHE) is LOW, then data from I/O pins (I/O 9 High speed through I/O ) is written into the location specified on the address 16 t = 15 ns pins (A through A ). AA 0 14 Reading from the device is accomplished by taking Optimized voltage range: 2.5 V to 2.7 V chip enable (CE) and Output Enable (OE) LOW while forcing the Automatic power down when deselected write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins Independent control of upper and lower bits appears on I/O to I/O . If Byte High Enable (BHE) is LOW, then 1 8 CMOS for optimum speed and power data from memory appears on I/O to I/O . See the Truth Table 9 16 on page 11 for a complete description of read and write modes. Package offered: 44-pin TSOP II The input/output pins (I/O through I/O ) are placed in a high 1 16 impedance state when the device is deselected (CE HIGH), the Functional Description outputs are disabled (OE HIGH), the BHE and BLE are disabled The CY7C1020CV26 is a high performance CMOS static RAM (BHE, BLE HIGH), or during a write operation organized as 32,768 words by 16 bits. This device has an (CE LOW, and WE LOW). automatic power down feature that significantly reduces power The CY7C1020CV26 is available in a standard 44-pin TSOP consumption when deselected. Type II. For a complete list of related documentation, click here. Logic Block Diagram Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05406 Rev. *G Revised September 14, 2015