64K x 32 IDT71V632/Z 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features with full support of the Pentium and PowerPC processor interfaces. 64K x 32 memory configuration The pipelined burst architecture provides cost-effective 3-1-1-1 second- Supports high system speed: ary cache performance for processors up to 117MHz. Commercial: The IDT71V632 SRAM contains write, data, address, and control A4 4.5ns clock access time (117 MHz) registers. Internal logic allows the SRAM to generate a self-timed write Commercial and Industrial: based upon a decision which can be left until the extreme end of the write 5 5ns clock access time (100 MHz) cycle. 6 6ns clock access time (83 MHz) The burst mode feature offers the highest level of performance to the 7 7ns clock access time (66 MHz) system designer, as the IDT71V632 can provide four cycles of data for Single-cycle deselect functionality (Compatible with a single address presented to the SRAM. An internal burst address counter Micron Part MT58LC64K32D7LG-XX) accepts the first cycle address from the processor, initiating the access LBO input selects interleaved or linear burst mode sequence. The first cycle of output data will be pipelined for one cycle before Self-timed write cycle with global write control (GW), byte it is available on the next rising clock edge. If burst mode operation is write enable (BWE), and byte writes (BWx) selected (ADV=LOW), the subsequent three cycles of output data will be Power down controlled by ZZ input available to the user on the next three rising clock edges. The order of these Operates with a single 3.3V power supply (+10/-5%) three addresses will be defined by the internal burst counter and the LBO Packaged in a JEDEC Standard 100-pin rectangular plastic input pin. thin quad flatpack (TQFP). The IDT71V632 SRAM utilizes IDT s high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x Description 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32 in both desktop and notebook applications. Pin Description Summary A0A15Atddress Inputs Isnpu Synchronou CECthip Enable Isnpu Synchronou CS0, CS1Cthips Selects Isnpu Synchronou OEOtutput Enable Isnpu Asynchronou Gtlobal Write Enable Isnpu Synchronou GW BWEBtyte Write Enable Isnpu Synchronou Itndividual Byte Write Selects Isnpu Synchronou BW1, BW2, BW3, BW4 CkLKCtloc IAnpu N/ ADVBturst Address Advance Isnpu Synchronou Atddress Status (Cache Controller) Isnpu Synchronou ADSC Atddress Status (Processor) Isnpu Synchronou ADSP LBOLtinear / Interleaved Burst Order ICnpu D ZeZStleep Mod Isnpu Asynchronou I/O0I/O31DOata Input/Output Is/ Synchronou VDD, VDDQ3r.3V PAowe N/ VSS, VSSQArrray Ground, I/O Ground PAowe N/ 3619 tbl 01 Pentium processor is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc. MAY 2010 1 2010 Integrated Device Technology, Inc. DSC-3619/07IDT71V632, 64K x 32, 3.3V Synchronous SRAM with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges (1) Pin Definitions SnymbolPOin Functio Ie/ Anctiv Descriptio A0A15AIddress Inputs N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. ADSC Address Status IWL.O Synchronous Address Status from Cache ControllerADSC is an active LOW (Cache Controller) input that is used to load the address registers with new addresses. ADSC is NDOTGyATE b CE. Synchronous Address Status from Processor. ADSP is an active LOW input that Address Status IWLO ADSP is used to load the address registers with new addresses. ADSP is gated by (Processor) CE. ADVBIurst Address AdvanceL.OW Synchronous Address Advance ADV is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When this input is HIGH the burst counter is not incremented that is, there is no address advance. BIyte Write EnableLsOW Synchronous byte write enable gates the byte write input BW1BW4. If BWE is BWE LOW at the rising edge of CLK then BWX inputs are passed to the next stage in the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. Individual Byte IWL.O Synchronous byte write enables BW1 controls I/O(7:0), BW2 controls I/O(15:8), BW1BW4 Write Enables etc. Any active byte write causes all outputs to be disabled. ADSP LOW disables all byte writes. BW1BW4 must meet specified setup and hold times with respect to CLK. CIhip Enable L.OW Synchronous chip enable CE is used with CS0 and CS1 to enable the CE IDT71V632. CE also gates ADSP. CkLKCIloc N/A This is the clock input. All timing references for the device are made with respect to this input. CS0CIhip Select 0 HSIGH Synchronous active HIGH chip select. C 0 is used with CE and CS1 to enable the chip. CIhip Select 1 L.OW Synchronous active LOW chip select CS1 is used with CE and CS0 to enable CS1 the chip. Synchronous global write enable. This input will write all four 8-bit data bytes GIlobal Write Enable LOW GW when LOW on the rising edge of CLK. GW supercedes individual byte write enables. I/O0I/O31DOata Input/Output IA/ N/ Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered by the rising edge of CLK. LBOLIinear Burst OrderLnOW Asynchronous burst order selection DC input. Whe LBO is HIGH the Interleaved (Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst sequence is selected. LBO is a static DC input and must not change state while the device is operating. OIutput Enable LnOW Asynchronous output enable. Whe OE is LOW the data output drivers are OE enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedence state. VDDPAower Supply NA/N./ 3.3V core power supply inputs VDDQPAower Supply NA/N./ 3.3V I/O power supply inputs VSSGAround NA/N./ Core ground pins VSSQGAround NA/N./ I/O ground pins NtCNAo Connec NA/N./ NC pins are not electrically connected to the chip ZeZSIleep Mod HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V632 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. 3619 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422