64K x 32 71V632 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features 64K x 32 memory configuration Self-timed write cycle with global write control (GW), byte Supports high system speed: write enable (BWE), and byte writes (BWx) Commercial and Industrial: Power down controlled by ZZ input 5 5ns clock access time (100 MHz) Operates with a single 3.3V power supply (+10/-5%) 6 6ns clock access time (83 MHz) Packaged in a JEDEC Standard 100-pin rectangular plastic 7 7ns clock access time (66 MHz) thin quad flatpack (TQFP) Single-cycle deselect functionality Green parts available, see ordering information LBO input selects interleaved or linear burst mode Functional Block Diagram LBO ADV INTERNAL Burst ADDRESS CE Sequence CLK 2 Burst 64K x 32 Binary Logic 16 BIT Counter ADSC A0* Q0 MEMORY CLR . A1* ARRAY Q1 ADSP 2 CLK EN A0, A1 A2A15 ADDRESS A0A15 32 32 REGISTER 16 GW BWE Byte 1 Write Register Byte 1 Write Driver BW1 8 Byte 2 Write Register Byte 2 Write Driver BW2 8 Byte 3 Byte 3 Write Register Write Driver BW3 8 Byte 4 Byte 4 Write Register Write Driver BW4 8 OUTPUT REGISTER CE Q D CS0 Enable DATA INPUT CS1 Register REGISTER CLK EN Powerdown ZZ DQ Enable Delay Register OE OUTPUT BUFFER OE 32 I/O0I/O31 3619 drw 01 1 Mar.09.2071V632, 64K x 32, 3.3V Synchronous SRAM with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges a single address presented to the SRAM. An internal burst address counter Description accepts the first cycle address from the processor, initiating the access The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32 sequence. The first cycle of output data will be pipelined for one cycle before with full support of the Pentium and PowerPC processor interfaces. it is available on the next rising clock edge. If burst mode operation is The pipelined burst architecture provides cost-effective 3-1-1-1 second- selected (ADV=LOW), the subsequent three cycles of output data will be ary cache performance for processors up to 100MHz. available to the user on the next three rising clock edges. The order of these The IDT71V632 SRAM contains write, data, address, and control three addresses will be defined by the internal burst counter and the LBO registers. Internal logic allows the SRAM to generate a self-timed write input pin. based upon a decision which can be left until the extreme end of the write The IDT71V632 SRAM utilizes a high-performance, high-volume cycle. 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x The burst mode feature offers the highest level of performance to the 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density system designer, as the IDT71V632 can provide four cycles of data for in both desktop and notebook applications. Pin Description Summary A0A15Atddress Inputs Isnpu Synchronou CECthip Enable Isnpu Synchronou CS0, CS1Cthips Selects Isnpu Synchronou Otutput Enable Isnpu Asynchronou OE Gtlobal Write Enable Isnpu Synchronou GW BWEBtyte Write Enable Isnpu Synchronou Itndividual Byte Write Selects Isnpu Synchronou BW1, BW2, BW3, BW4 CkLKCtloc IAnpu N/ ADVBturst Address Advance Isnpu Synchronou Atddress Status (Cache Controller) Isnpu Synchronou ADSC ADSPAtddress Status (Processor) Isnpu Synchronou Ltinear / Interleaved Burst Order ICnpu D LBO ZeZStleep Mod Isnpu Asynchronou I/O0I/O31DOata Input/Output Is/ Synchronou VDD, VDDQ3r.3V PAowe N/ VSS, VSSQArrray Ground, I/O Ground PAowe N/ 3619 tbl 01 Pentium processor is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc. 6.422 Mar.09.20