Clk 128K x 36 71V2556S 71V2556SA 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features 128K x 36 memory configurations Individual byte write (BW1 - BW4) control (May tie active) Supports high performance system speed - 166 MHz Three chip enables for simple depth expansion (3.5 ns Clock-to-Data Access) 3.3V power supply (5%), 2.5V I/O Supply (VDDQ) TM ZBT Feature - No dead cycles between write and read Optional - Boundary Scan JTAG Interface (IEEE 1149.1 cycles complaint) Internally synchronized output buffer enable eliminates the Packaged in a JEDEC standard 100-pin plastic thin quad need to control OE flatpack (TQFP) and 119 ball grid array (BGA) Single R/W (READ/WRITE) control pin Industrial temperature range (40C to +85C) is available Positive clock-edge triggered address, data, and control for selected speeds signal registers for fully pipelined applications Green parts available, see ordering information 4-word burst capability (interleaved or linear) Functional Block Diagram LBO 128Kx36 BIT MEMORY ARRAY Address A 0:16 DQ Address CE1, CE2, CE2 R/W DQ Control CEN DI DO ADV/LD BWx DQ Control Logic Clk Mux Sel D Clock Output Register Q Gate OE , 4875 drw 01a TMS Data I/O 0:31 , JTAG TDI I/O P 1:4 TDO (SA Version) TCK TRST (optional) ZBT and ZeroBus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc. 1 Aug.20.20 Input Register71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges There are three chip enable pins (CE1, CE2, CE2) that allow the user Description to deselect the device when desired. If any one of these three are not The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) asserted when ADV/LD is low, no new memory operation can be initiated. synchronous SRAM. It is designed to eliminate dead bus cycles when However, any pending data transfers (reads or writes) will be completed. turning the bus around between reads and writes, or writes and reads. TM The data bus will tri-state two cycles after chip is deselected or a write is Thus, they have been given the name ZBT , or Zero Bus Turnaround. initiated. Address and control signals are applied to the SRAM during one clock The IDT71V2556 has an on-chip burst counter. In the burst mode, the cycle, and two cycles later the associated data cycle occurs, be it read IDT71V2556 can provide four cycles of data for a single address or write. presented to the SRAM. The order of the burst sequence is defined by the The IDT71V2556 contains data I/O, address and control signal LBO input pin. The LBO pin selects between linear and interleaved burst registers. Output enable is the only asynchronous signal and can be used sequence. The ADV/LD signal is used to load a new external address to disable the outputs at any given time. (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = A Clock Enable (CEN) pin allows operation of the IDT71V2556 to be HIGH). suspended as long as necessary. All synchronous inputs are ignored The IDT71V2556 SRAM utilizes a high-performance CMOS process when (CEN) is high and the internal device registers will hold their previous and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic values. quad flatpack (TQFP) as well as a 119 ball grid array (BGA). Pin Description Summary A0-A16Atddress Inputs Isnpu Synchronou Cthip Enables Isnpu Synchronou CE1, CE2, CE2 Otutput Enable Isnpu Asynchronou OE R/WRtead/Write Signal Isnpu Synchronou Ctlock Enable Isnpu Synchronou CEN Itndividual Byte Write Selects Isnpu Synchronou BW1, BW2, BW3, BW4 CkLKCtloc IAnpu N/ ADV/LDAtdvance burst address / Load new address Isnpu Synchronou Ltinear / Interleaved Burst Order Icnpu Stati LBO TtMSTtest Mode Selec Isnpu Synchronou TtDITtest Data Inpu Isnpu Synchronou TkCKTtest Cloc IAnpu N/ TtDOTtest Data Outpu Osutpu Synchronou JtTAG Reset (Optional) Isnpu Asynchronou TRST ZeZStleep Mod Isnpu Synchronou I/O0-I/O31, I/OP1-I/OP4DOata Input / Output Is/ Synchronou VDD, VDDQCyore Power, I/O Power Scuppl Stati VSSGyround Scuppl Stati 4875 tbl 01 6.422 Aug.20.20